Intel delays mass production of 10nm CPUs to 2019
- Thread starter mbello
- Start date
From what I have heard Xilinx 7nm has been delayed as well. You may see samples in 2019 but HVM is closer to 2020.
Today the Intel 14nm FPGA is superior to Xilinx 16nm in price, performance, and density. It also resides on one die where as Xilinx uses multiple die. Intel will also release the highest capacity FPGA very soon.
You are probably right about Intel 10nm FPGAs being delayed but the process gap between Intel and Xilinx is not as big as you might think. I also think the Intel 10nm FPGAs will again beat Xilinx, just my opinion of course.
At the TSMC Symposium yesterday 7nm and 5nm were front and center. 10nm and 7 EUV not so much so my expectation is that most people will skip 7 EUV, including Apple. 7nm is in HVM today with more than 50 tape-outs expected in 2018 and 5nm will start risk production in 1H 2019. 5NM will use EUV and offer a +15% performance advantage or a +30% power advantage over 7nm. Density is 1.8X.
3NM will use nanowires and nano sheet. Scott covered it nicely here: IEDM 2017 - imec Charting the Future of Logic
TSMC Symposium blogs will be coming shortly including Tom Dillinger's Top 10. Here is last year's: Top 10 Updates from the TSMC Technology Symposium, Part I
It was a great conference. I'm a big fan of the new CEO CC Wei. He is brilliant and quite funny, a rare combination, absolutely!
Depends on how you designed your chips.
If your guiding philosophy was essentially speed demon, then you have a problem.
If your guiding philosophy was essentially brainiac, then you get to throw more smarts at the CPU.
And of course throughput processors care mainly about the number of transistors.
In other words
Throughput:
- IBM is fine with the same speed and more cores on die, each "core" an ever stranger multi-headed mult-threaded weirdness that exists purely to get around software licensing.
- nV is fine with more transistors at the same speed.
Latency:
- Apple is clearly in the super-brainiac camp, and no evidence yet that they're running out of smarts.
- ARM/QC are less aggressively brainiac, but clearly in that camp and clearly able to pivot to a more brainiac stance.
- Intel. Ah, yes, THAT is the company that has a problem.
They seem aggressively INCAPABLE of converting more transistors into higher single-threaded performance, and so have bet aggressively on high frequencies. And that's turning out to be a problematic bet...
Maybe that's why they're pushing EMIB so hard? The backup strategy at some point (when they finally get their ducks in a row) is to move the part that can benefit from small transistors (iGPU) to 10nm while the core chugs on at 14nm++++?
Just remember that any process which uses EUV for all critical layers like TSMC 5nm (7+ will only use EUV for a few layers) will need *huge* numbers of high-throughput EUV steppers to be usable for Apple-type volumes, and *must* be cost-competitive. This is a very big step forward in both throughput and available number of machines from where ASML are right now, or where they will be if 5nm enters risk production in 1H 2019. If nothing else, the bottleneck is likely to be the speed at which Zeiss can manufacture the optics, especially the high-NA anamorphic ones needed for cost-competitive 5nm and beyond.
This isn't just a TSMC issue, it's an issue for the entire industry at the next node -- there's no point spending an absolute fortune to develop an EUV-only process that can't address the biggest volume "fill-the-fabs" applications when the market needs them because of equipment supply bottlenecks. Which also means if you get your EUV stepper orders in first and book out most of the ASML capacity your competitors are screwed...
Very true. EUV is not HVM worthy as of yet which is why I think TSMC 7nm will own the market for quite some time. TSMC said EUV is running in fab at 145w. They need to get that up to 250w reliably for HVM which to me is 2019.
Samsung Foundry Day is May 22, we should know more then.
Interesting. From what i heard, they are really cheaper (significantly) but XCVU440 can still emulate 50% more ASIC gates. 2.5D might be problem but when it is considered in design then it might not have impact (single block is quite large). Intel's advantage on the other hand is hardened floating point blocks and maybe more aggressive hyperpipelining. Off course it is just what i heard.
Latest rumor points to 10nm HVM being actually delayed into 2020
https://twitter.com/TMFChipFool/status/9960097431593820...
Anyone has any insight on that?
<figure class="usrProfile"><figcaption class="line infosHold lzBtn" data-lztpl="" data-route=""></figcaption> </figure>
https://twitter.com/TMFChipFool/status/9960097431593820...
Anyone has any insight on that?
<figure class="usrProfile"><figcaption class="line infosHold lzBtn" data-lztpl="" data-route=""></figcaption> </figure>
hist78
Well-known member
Can Intel just stop predicting the 10nm HVM date after all their past predictions didn't come true? It's meaningless and can lead to even more dangerous habits.
Intel still has not learned the transparency lesson. In this day and age you can run but you cannot hide....
Intel 10nm is pretty much a disaster. There are multiple sources now indicating that 10nm from Intel will arrive in 2020. The entire management at Intel needs to take responsibility for this debacle. I think Brian Krzanich will be gone by the time AMD ships 7nm Rome sometime in H1 2019. Intel is going to bleed share rapidly in servers which is their highest margin business. I expect Intel will go through major reorganization and huge layoffs by 2020. If Intel 7nm does not arrive in time to compete with foundry 3nm (sometime in H1 2022) then they will be forced to go fabless. Its going to be gut wrenching to watch 2019 and 2020 unfold if you are Intel shareholder or employee.
Then the big question is how Intel's 7nm process is coming along? This question should be in everyone's mind yet I could not find any mention of it from Intel (not that we would have any reason to believe what Intel has to say about it).
This is where their lack of transparency will bite them, when it becomes clear to everyone how critical it will be for Intel to deliver 7nm in time, investors will have lost confidence in BK's words and he will be out (probably taking many others with him).
They clearly lost the race to 7/10nm and will suffer a lot from it, but is there any hope they will become competitive again for 5/7nm?
This is where their lack of transparency will bite them, when it becomes clear to everyone how critical it will be for Intel to deliver 7nm in time, investors will have lost confidence in BK's words and he will be out (probably taking many others with him).
They clearly lost the race to 7/10nm and will suffer a lot from it, but is there any hope they will become competitive again for 5/7nm?
Unfortunately it will be some time before EUV is ready for HVM for a full EUV implementation. TSMC is starting with a limited amount of layers to get the throughput/yield needed to run their business at a profit. Samsung is implementing more layers on their 7nm but Samsung has never really let bad yield stop them since they have no transparency in their foundry operations.
Intel on the other hand will do a full EUV implementation at 7nm and they will not release it until yield is >80% (my opinion). That could push Intel 7nm out to 2022. There is no doubt that Intel will have the "best" EUV implementation at 7nm just like Intel has the best 14nm FinFet implementation but the best does not count for much when you are years late.
I have done quite a bit of due diligence on EUV design inside the ecosystem and the only company I can find that is actively doing EUV design is QCOM and that is for Samsung 7nm. Even though Samsung says 7nm production will happen in June my sources say in reality it will be 1H 2019.
In my opinion most TSMC customers will skip 7+EUV for 5nm EUV and will start designing later this year for production in 2020 (Apple will be first). Apple will do an optimized 7nm chip for A13 in 2019 (A12 is also 7nm) like they did at 16nm for the A9 and A10.
Sound reasonable?
What's really hurting Intel is not the delay itself, but how the delay happened. It got postponed 3 times and each time a stop gap solution got shoved in - Kaby lake /coffee lake/ cascade lake. If they knew from the beginning that 10nm would be delayed 3 years, then they would have had time to design a proper Skylake update with real architecture improvements
Today I read another piece published at Anandtech where they list the latest forecast from Samsung:Samsung Foundry Roadmap: EUV-Based 7LPP for 2018, 3 nm Incoming
It lists 8LPP as going HVM now or very soon and 7LPP available for internal use 2Q2018 and HVM in 1Q2019. Same story for 5LPE, internal use in 2Q2019, HVM in 1Q2020.
What I found interesting is that nowhere they talk about speed improvement, it is all about power. I remember reading a piece on Samsung's 8LPP and there too it had claims for -10% power and a question mark for perf improvement. This goes in line with Scotten's article where transistor performance for Intel's 10nm and 10+nm were forecasted to be lower than current 14++nm.
If 10nm and 7nm are mostly about power, they will be most useful on very large (server) processors that today are more limited by thermals than transistor performance. However, those large processors need very good yield to become viable. Therefore, AMD seems to be well positioned with their CCX architecture where they combine smaller dies to make large processors. I believe Intel will have to copy AMD and that is maybe why Jim Keller was brought over to Intel.
The article linked above also has an interesting part about Samsung's 3nm "multi-bridge-channel FETs":
[h=3]"3 nm to Use GAAFETs[/h]The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung’s own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.
MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung’s fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the EUV in general will have a clear impact on Samsung’s technologies several years down the road."
It lists 8LPP as going HVM now or very soon and 7LPP available for internal use 2Q2018 and HVM in 1Q2019. Same story for 5LPE, internal use in 2Q2019, HVM in 1Q2020.
What I found interesting is that nowhere they talk about speed improvement, it is all about power. I remember reading a piece on Samsung's 8LPP and there too it had claims for -10% power and a question mark for perf improvement. This goes in line with Scotten's article where transistor performance for Intel's 10nm and 10+nm were forecasted to be lower than current 14++nm.
If 10nm and 7nm are mostly about power, they will be most useful on very large (server) processors that today are more limited by thermals than transistor performance. However, those large processors need very good yield to become viable. Therefore, AMD seems to be well positioned with their CCX architecture where they combine smaller dies to make large processors. I believe Intel will have to copy AMD and that is maybe why Jim Keller was brought over to Intel.
The article linked above also has an interesting part about Samsung's 3nm "multi-bridge-channel FETs":
[h=3]"3 nm to Use GAAFETs[/h]The most advanced process technologies that Samsung announced this week are the 3GAAE/GAAP (3nm gate-all-around early/plus). Both will rely on Samsung’s own GAAFET implementation that the company calls MBCFET (multi-bridge-channel FETs), but again, Samsung is not elaborating on any details. The only thing that it does say is that the MBCFET has been in development since 2002, so it will have taken the tech at least twenty years to get from an early concept to production.
MBCFETs are intended to enable Samsung to continue increasing transistor density while reducing power consumption and increasing the performance of its SoCs. Since the 3GAAE/GAAP technologies are three or four generations away, it is hard to make predictions about their actual benefits. What is safe to say is that the 3GAAE will be Samsung’s fifth-generation EUV process technology and therefore will extensively use appropriate tools. Therefore, the success of the EUV in general will have a clear impact on Samsung’s technologies several years down the road."
The EUV line is not even constructed yet: Samsung Electronics Breaks Ground on New EUV Line in Hwaseong – Samsung Global Newsroom
"The new facility is expected to be completed within the second half of 2019 and start production ramp-up in 2020. The initial investment in the new EUV line is projected to reach USD 6 billion by 2020 and additional investment will be determined depending on market circumstances."
That is an expansion of the alredy existing one.