siliconbruh999
Well-known member
External?couple points:
Intel had a press conference stating that they sampled a product that will be releases in 2nd half 2025
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External?couple points:
Intel had a press conference stating that they sampled a product that will be releases in 2nd half 2025
Sorry, I was just reflecting what was in the article. It is not anything new, Just a press event "delivering" Samples. Which means it is ~one year from launch.External?
No worries so Q3 is most likely for the first 18ASorry, I was just reflecting what was in the article. It is not anything new, Just a press event "delivering" Samples. Which means it is ~one year from launch.
couple points:
Intel had a press conference stating that they sampled a product that will be releases in 2nd half 2025.
Intel cannot capture "manufacturing margin" when their manufacturing has negative margin.
Intels cost issues are not yields, it is output per tool. The yield by they time this ramps to more than 20K wafers per month (2026) will be fine and competitive.
reminder: Ramping a new technology and fab ALWAYS lowers margin for 6-12 months. It is broken out that way on every earnings report for the last 20 years.
Intel gets less wafers out per tool. EUV is not the biggest issue. This is do to inefficient operations (scale) and to inefficient processes (Dep time, etch times, PMs, Engineering wafers, inability to use all chambers on a cluster tool. complexity of operations. Our model for output by fab today shows they get about half they output (full capacity) of Production wafers compared to what TSMC would get. The CFO has very accurately reported on why this happens. What you do when you have leading products on leading processes with no competition is different than what happens in a competitive environment.To be clear I am not saying Intel's inability to make money is due to yield. I'm saying that what Intel considers an acceptable yield when HVM starts is different from what TSMC considers acceptable at that point in time. Both companies will increase yields after HVM starts, and I believe Intel probably matches TSMC yields at some point, just not when HVM starts. So I am saying foundry customers expect TSMC yield levels when they start their products and Intel doesn't provide those yield levels at the time they have launched internal products for HVM.
If you take Intel at their word, then the reason they have negative manufacturing margins is primarily because (at least the way I read their public statements):
1) processes are being priced competitively based on PPA and none of their processes have PPA comparable to the cutting edge at TSMC where they are currently making their processors. As a result they are pricing those nodes significantly below what they will charge for 18A
2) the cost of bring on all that fab capacity (which I think was more than a little over ambitious).
Ramping 18A will be expensive, but if the process is competitive then Intel should be able to ramp it profitably. The cost of the capacity build out will continue to weigh on manufacturing margins for several more years.
I think your point about costs being related to tool utilization is interesting. Are you referring to the need for quadruple patterning due to not using EUV (i.e. more process steps for a comparable outcome)?
Otherwise, this would imply that either Intel engineers either don't know how to write efficient recipes or don't know how to maintain their tools and keep them in production or that Intel doesn't buy the right mix of tools and creates unnecessary production bottlenecks.
If you are not referring to the failure to move to EUV then I'm more inclined to believe that Intel's process flows just aren't as efficient as they need to be because I don't think Intel engineers are generally incompetent.
I think that the hesitancy to believe Intel on 18A stems from their history of statements over the past few years. Lots of us still remember the 10+++++++ fiasco quite well. As a result, lots of people are all to ready to believe that Intel is having issues with 18A. Intel dropping 20A at the last possible public moment didn't really help their story either.I don't really get it why so many articles are repeating the same mantra "Intel’s struggle with yield rates in its 18A process has been well documented", when Intel's been constantly repeating that 18A is ok. Is there actually any credible source of Intel's 18A yield struggle? If anything, there were some rumors on Twitter about 18A being quite good.
I believe that Intel's biggest issue is one of politics. The view of many is that Intel's day is past. Intel keeps providing financial evidence quarter after quarter to reinforce this belief. My personal thoughts are that if Intel can regain process leadership with 18A, they will be on the right track in 2025, but their financials will not show it much until 2027 IMO. Can Intel hang on to the politics of this until then?Intel gets less wafers out per tool. EUV is not the biggest issue. This is do to inefficient operations (scale) and to inefficient processes (Dep time, etch times, PMs, Engineering wafers, inability to use all chambers on a cluster tool. complexity of operations. Our model for output by fab today shows they get about half they output (full capacity) of Production wafers compared to what TSMC would get. The CFO has very accurately reported on why this happens. What you do when you have leading products on leading processes with no competition is different than what happens in a competitive environment.
Right now the biggest issue is scale. 18A current planned loadings are not even one full fab until end of 2026. How do you build out a fab if you cannot load it? If a product is already running in TSMC, redesigning it to run in Intel is a lot of money with no return. Until Intel gets 1 full Fab of External foundry, This challenge does not go away. We have lots of spreadsheets to show the challenges
GAA and BSP is probably the biggest change in 20+ years. Intel says they are even with TSMC. We will know in next year whether Intel Delivers cost effectively.
The other issue I see is the closer we get to 18A, the lower the claims about its metrics become. TSMC's N2 will be out shortly after 18A (at least that is how I have it in my head right now). Should 18A be more equal to TSMC N3P than TSMC N2, TSMC can continue to charge a premium for its newest process and force Intel to sell its 18A for less.
Just a nit, but I believe it was 14++++++++, though 10nm was the fiasco.I think that the hesitancy to believe Intel on 18A stems from their history of statements over the past few years. Lots of us still remember the 10+++++++ fiasco quite well.
10 nm repeated 14nm+++++Just a nit, but I believe it 14++++++++, though 10nm was the fiasco.
I'm really interested in your view on Intel buying high NA machines. Rumors are that they bought almost whole 2024 high NA allocation from ASML. Why would they buy 4 or 5 high NA machines now? Each costs 400 million, which could be much better used on 18A ramp, no? I understand they need 1 or 2 high NA for 14A development, but why buy so many? Also, these high NA machines will be standing in the lab doing nothing profitable for at least 2-3 years, if they ever ramp 14A...Good Point. Originally 20A was supposed to be even with TSMC, 18A much better. That has changed on Intel announcements. I do expect 18A to be PPA comparable to TSMC N2.
But lets assume 18A is on track and is the best process (best case). where will they make it? What will the foundry volume of this Fab be? The Financial numbers are problematic.
I didn't count the plus signs; I was just mimicking OneEng. As for 10nm, the plus versions seemed to be the least of Intel's problems with that generation.10 nm repeated 14nm+++++
you put too many plus there original was in Broadwell 5th gen than 6th gen skylake all the way to 11 th gen we had 2 gen using same 14nm so it should be 14nm+++++.
Also we had 10nm original 10nm cannon lake not worth buying
Ice lake 10nm+
tiger lake 10nm++(10 nm SuperFin) than Alder lake 10nm+++ and than
raptor lake 10nm++++
IMO:I'm really interested in your view on Intel buying high NA machines. Rumors are that they bought almost whole 2024 high NA allocation from ASML. Why would they buy 4 or 5 high NA machines now? Each costs 400 million, which could be much better used on 18A ramp, no? I understand they need 1 or 2 high NA for 14A development, but why buy so many? Also, these high NA machines will be standing in the lab doing nothing profitable for at least 2-3 years, if they ever ramp 14A...
It was both, but I exaggerated the number of "+" as a jest.Just a nit, but I believe it was 14++++++++, though 10nm was the fiasco.
Another good point. Again, I see Intel getting ahead of themselves.IMO:
High NA will not win the war. Intel is not cornering the market on high NA. TSMC will get high NA when they need it. Samsung has larger problems
Note: Intel did not buy all those tools. They put in an order or reservation. Orders can be delayed or cancelled depending on lead time. Checks are not written yet for most of them.
Intel will not have high NA tools sitting idle. guaranteed.
The press is overblowing the whole high NA plan. We dont know what the terms of the agreements are. we dont know how the tools will perform on future processes.
I think that the hesitancy to believe Intel on 18A stems from their history of statements over the past few years. Lots of us still remember the 10+++++++ fiasco quite well. As a result, lots of people are all to ready to believe that Intel is having issues with 18A. Intel dropping 20A at the last possible public moment didn't really help their story either.
I believe that Intel's biggest issue is one of politics. The view of many is that Intel's day is past. Intel keeps providing financial evidence quarter after quarter to reinforce this belief. My personal thoughts are that if Intel can regain process leadership with 18A, they will be on the right track in 2025, but their financials will not show it much until 2027 IMO. Can Intel hang on to the politics of this until then?
The other issue I see is the closer we get to 18A, the lower the claims about its metrics become. TSMC's N2 will be out shortly after 18A (at least that is how I have it in my head right now). Should 18A be more equal to TSMC N3P than TSMC N2, TSMC can continue to charge a premium for its newest process and force Intel to sell its 18A for less.
Finally, TSMC has so much more capacity than Intel that it would take quite some time for Intel to ramp up new lines for 18A foundry services for other customers. Intel can't simply go with the "if you build it, they will come" philosophy anymore. The politics and financials won't allow it.
Don't get me wrong, I seriously want Intel to succeed. I have also seen them step in poo before, then put the other foot in the poo, then wallow in it a while, then finally come out clean in the wash. Hopefully this time will be the same.
I agree though I'll add some of the "future tech" stuff is probably keeping the stock price from being in an even worse situation. They need to dangle some carrots too to keep the price up while they have ugly 2024-2025-2026 financials.. (If Intel didn't have dividends, each 10nm delay would have substantially impacted the stock price)."My personal thoughts are that if Intel can regain process leadership with 18A, they will be on the right track in 2025, but their financials will not show it much until 2027 IMO. Can Intel hang on to the politics of this until then?"
In the next 4–5 years, Intel’s biggest challenge won’t be process leadership. In my opinion, the strength of Intel’s products and finances (profit, revenue, expenses, cash flow) is more important than process leadership. Delivering competitive products that the market demands—whether they are made in-house or by external foundries—is the most crucial objective Intel needs to focus on. This likely has more potential than seeking external customers for Intel Foundry.
Intel is, at its core, a product company. It generates most of its revenue and profit from its products.
I understand the concern's given Intel's track record over the last decade. They are deservedly in a place where they need to walk the walk with very little taken on faith.It was both, but I exaggerated the number of "+" as a jest.
My point is that Intel has had a horrendous track record of meeting their process commitments since the proposed introduction timing of 10nm (thus the start of the 14+++ fiasco).
For Intel, moving to GAA, and BSPD seems very risky to me. Also EUV is very new to Intel.
I do get that Intel is behind and very much wants to be ahead. I worry that they will get out over their skies again with 18A. They could find that they can, in fact, make 18A chips, but that the yields and cost are not competitive. In this case, a "Win" may embolden them to continue down a bad path. "In for a penny, in for a pound".
Another good point. Again, I see Intel getting ahead of themselves.
From a strategic standpoint, it seems that it would be difficult for an IDM to best a pure foundry company on being a foundry.
Did I miss something? Has Intel said anything that contradicts these claims? Or was there an earlier slide that showed something different with 20A?Good Point. Originally 20A was supposed to be even with TSMC, 18A much better. That has changed on Intel announcements. I do expect 18A to be PPA comparable to TSMC N2.
But lets assume 18A is on track and is the best process (best case). where will they make it? What will the foundry volume of this Fab be? The Financial numbers are problematic.
Yes IDM2.0 Announcements were made to analysts in 2021. That was 3 years before this slide. But its a moot point since intel moved its 20A product to TSMC N3 and qualcomm cancelled its planned 20A product. Hence there is no 20A to compareDid I miss something? Has Intel said anything that contradicts these claims? Or was there an earlier slide that showed something different with 20A?
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