ICCAD 2015 - Call for Papers

[Daniel Payne]

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| style="padding: 4px 8px; border: 0px; outline: 0px; vertical-align: top; font-family: inherit; font-size: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit" | Deadline for Electronic Submission of Abstracts:
Friday, April 17, 2015
5:00pm Pacific Daylight Time (GMT-7)
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Friday, April 24, 2015
5:00pm Pacific Daylight Time (GMT-7)
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View attachment 13016
ORIGINAL TECHNICAL SUBMISSIONS ON, BUT NOT LIMITED TO, THE FOLLOWING TOPICS ARE INVITED:
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| style="padding: 4px 8px; border: 0px; outline: 0px; vertical-align: top; font-family: inherit; font-size: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit" | 1) SYSTEM-LEVEL CAD
1.1 System Design:

• System-level specification, modeling, and simulation
• System design flows and methods
• HW/SW co-design, co-simulation, co-optimization,
• and co-exploration
• HW/SW platforms for rapid prototyping
• System design case studies and applications
• System-level issues for 3D integration
• Micro-architectural transformation
• Memory architecture and system synthesis
• System communication architecture
• Network-on-chip design methodologies and CAD
• Network-on-chip design case studies and prototyping

1.2 Embedded Systems Hardware:

• Multi-core/multi-processors systems
• HW/SW co-design for embedded systems
• Static and dynamic reconfigurable architectures
• Memory hierarchies and management
• System-level consideration of custom storage architectures
• (flash, phase change memory, STT-RAM, etc.)
• Application-specific instruction-set processors (ASIPs)
• Hardware-based security (CAD for PUF’s, RNG, AES etc.)
• Detection and prevention of hardware Trojans
• Side-channel attacks, fault attacks and countermeasures
• Split manufacturing for security

1.3 Embedded Systems Software:

• Real-time software and operating systems
• Middleware and virtual machines
• Timing analysis and WCET
• Programming models for multi-core systems
• Profiling and compilation techniques
• Design exploration, synthesis, validation, verification, and optimization
• System software security techniques

1.4 Dark Silicon and Power/Thermal Considerations

• Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems
• Energy- and thermal aware application mapping and scheduling
• Energy- and thermal-aware dark silicon system design
• and optimization
• Run-time management for the dark silicon

1.5 Design Issues for Heterogeneous Computing

• Hardware-software partitioning of workloads
• High-level synthesis for heterogeneous computing
• Power/performance analysis of heterogeneous platforms
• Programming environment of heterogeneous computing
• Acceleration techniques including GPGPU, FPGA and specialized ASIC’s
• Application driven heterogeneous platforms for big data, machine learning etc.

2) SYNTHESIS, VERIFICATION, AND PHYSICAL DESIGN
2.1 High-Level, Behavioral, and Logic Synthesis and Optimization:

• High-level/Behavioral/Logic synthesis
• Technology-independent optimization and technology mapping
• Functional and logic timing ECO
• Resource scheduling, allocation, and synthesis
• Interaction between logic synthesis and physical design

2.2 Validation, Simulation, and Verification:

• High-level/Behavioral/Logic modeling and validation
• High-level/Behavioral/Logic simulation
• Formal, semi-formal, and assertion-based verification
• Equivalence and property checking
• Emulation and hardware simulation/acceleration
• Post-silicon functional validation

2.3 Cell-Library Design, Partitioning, Floorplanning, Placement:

• Cell-library design and optimization
• Transistor and gate sizing
• High-level physical design and synthesis
• Estimation and hierarchy management
• 2D and 3D partitioning, floorplanning, and placement
• Post-placement optimization
• Buffer insertion and interconnect planning

| style="padding: 4px 8px; border: 0px; outline: 0px; vertical-align: top; font-family: inherit; font-size: inherit; font-style: inherit; font-variant: inherit; font-weight: inherit; line-height: inherit" | 2.4 Network Synthesis, Routing, and Post-Layout Optimization and Verification:

• 2D and 3D clock network synthesis
• 2D and 3D global and detailed routing
• Package-/Board-level routing and chip-package-board co-design
• Post-layout/-silicon optimization

3) SOC ANALYSIS, SIMULATION AND TESTING
3.1 Design for Manufacturability:

• Process technology characterization, extraction, and modeling
• CAD for design/manufacturing interfaces
• CAD for reticle enhancement and lithography-related design
• Variability analysis and statistical design and optimization
• Yield estimation and design for yield
• Physical verification and design rule checking

3.2 Design for Reliability:

• Analysis and optimization for device-level reliability issues
• (stress, aging effects, ESD, etc.)
• Analysis for interconnect reliability issues
• (electromigration, thermal, etc)
• Reliability issues related to soft errors
• Design for resilience and robustness

3.3 Testing:

• Digital fault modeling and simulation
• Delay, current-based, low-power test
• ATPG, BIST, DFT, and compression
• Memory test and repair
• Core, board, system, and 3D IC test
• Post-silicon validation and debug
• Analog, mixed-signal, and RF test

3.4 Timing, Power Networks and Signal Integrity

• Deterministic and statistical static timing analysis and optimization
• Power and leakage analysis and optimization
• Circuit and interconnect-level low power design issues
• Power/ground network analysis and synthesis
• Signal integrity analysis and optimization

3.5 CAD for RF/analog, Multi-Domain Modeling and Interconnect

• CAD for analog, mixed-signal and RF
• CAD for mixed-domain (semiconductor, nanoelectronic, MEMS,
• and electro-optical) devices, circuits, and systems
• CAD for nanophotonics
• Device, interconnect and circuit extraction and simulation
• Package modeling and analysis
• EM simulation and optimization
• Behavior modeling of devices and interconnect
• Modeling of complex dynamical systems (molecular dynamics, fluid dynamics, computational finance, etc.)

4) CAD FOR EMERGING TECHNOLOGIES AND APPLICATIONS
4.1 Biological Systems and Bio-Electronics:

• CAD for biological computing systems
• CAD for synthetic biology
• Tools, methods and hardware for systems and computational biology
• CAD for bio-electronic devices, bio-sensors, MEMS, and systems

4.2 Nanoscale and Post-CMOS Systems:

• New device structures and process technologies
• New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.)
• Nanotechnologies, nanowires, nanotubes, graphene, etc.
• Quantum computing
• Optical devices and communication
• CAD for bio-inspired and neuromorphic systems

4.3 CAD for Cyberphysical Systems:

• CAD for internet-of-things and sensor networks
• CAD for automotive systems and power electronics
• Analysis and optimization of data centers
• CAD for display electronics
• Green computing (smart grid, energy, solar panels, etc.)

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SUBMISSION DETAILS​

Paper submissions must be made through the online submission system at the ICCAD web site. Regular papers will be reviewed as finished papers; preliminary submissions will be at a disadvantage.
Authors are asked to submit their work in two stages. In stage one (abstract submission), a title, abstract, and a list of all co-authors must be submitted via the ICCAD web submission site. In stage two (paper submission), the paper itself is submitted. Authors are responsible for ensuring that their paper submission meets all guidelines, and that the PDF is readable.

Deadline for Abstract Submissions
The submission abstract deadline is 5:00 pm Pacific Daylight Time (GMT -07:00), Friday April 17, 2015. No abstract submissions will be possible after this deadline.
Deadline for Paper Submissions
The submission paper deadline is 5:00 pm Pacific Daylight Time (GMT -07:00), Friday April 24, 2015.
We always have several authors contact the ICCAD office asking for a deadline extension. Due to the limited review cycle, NO extensions are granted for ANY reason.
REGULAR PAPER SUBMISSIONS

• All papers must be in PDF format only, with savable text.
• Each paper must be no more than 8 pages (including the abstract, figures, tables, and references), double-columned, 9pt or 10pt font.
• Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person.
• Submissions not adhering to these rules, or determined to be previously published (this includes pre-prints publicly available on personal or other websites, such as arXiv, or publicly available internal memoranda with author names divulged) or simultaneously submitted to another conference, or journal, will be summarily rejected. Internal memoranda with full content not publicly available, and with author names not divulged, may be submitted.

IMPORTANT: Final camera-ready versions must be identical to the submitted papers with the following exceptions; inclusion of author names/affiliation, correction of identified errors, addressing reviewer-demanded changes. No other modifications of any kind are allowed including modification of title, change of the author list, reformatting, restyling, rephrasing, removing figures/results/text, etc. The TPC Chairs reserve the right to finally reject any manuscripts not adhering to these rules. A report detailing all the revisions made must be submitted together with the final camera-ready manuscript once any revision is conducted.
TEMPLATES
Paper templates are available at the ICCAD website; authors are recommended to format their papers based on the templates.
NOTIFICATION OF ACCEPTANCE
Authors will be notified of acceptance on or before Monday, June 22, 2015. Final paper guidelines will be sent at that time.
PROCEEDINGS
The deadline for final papers is Wednesday, July 22, 2015. Accepted papers are allowed six pages in the conference proceedings free of charge. Each additional page beyond six pages is subject to the page charge at $150.00 per page up to the eight-page limit. ACM will hold the copyright for ICCAD 2015 proceedings. Authors of accepted papers must sign an ACM copyright release form for their paper.
CONFERENCE REGISTRATION
At least one author per accepted paper must register by Friday, September 4, 2015, at the discounted speaker’s registration rate. Failure to register will result in your paper being removed from the conference proceedings. IEEE reserves the right to exclude a paper from distribution after the conference (e.g., removal from IEEE Xplore) if the paper is not presented at the conference.
ACM/IEEE WILLIAM J. MCCALLA ICCAD BEST PAPER AWARD
Two papers, one from front-end and one from back-end, will be awarded with this prestigious award. The winners will be chosen from nominated papers after a thorough and competitive process by area-specific selection committees and announced at the opening session.
ICCAD TEN-YEAR RETROSPECTIVE MOST INFLUENTIAL PAPER AWARD
One paper from 2005 and 2006 editions of ICCAD will be selected for this outstanding recognition as evidenced by impact on the research community reflected in citations, on the vendor community via its use in an industrial setting, or by initiating new research venues during the past decade. Nominations from the community are welcome and can be sent to Sri Parameswaran, Technical Program Vice-Chair at sridevan@cse.unsw.edu.au.

If you need assistance, please contact the appropriate committee members:
General Chair:
Diana Marculescu, dianam@cmu.edu
Program Chair:
Frank Liu, frankliu@us.ibm.com
Vice-Program Chair:
Sri Parameswaran, sridevan@cse.unsw.edu.au
Tutorial and Special Session Chair:
Iris Bahar, [email]iris_bahar@brown.edu[/EMAIL]
Workshop Chair:
David Pan, [email]dpan@ece.utexas.edu[/EMAIL]​