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Hybrid Memory Cube cranks up to 11! err,... I mean 30!

M

msporer

Guest
The HMC Consortium today released their next version specification supporting 30G serial links, doubling the IO rate but at the same time going from an SR (15dB loss) channel to a VSR (10dB) channel.

While the IO bandwidth doubles from 240GB/s to 480GB/s, the internal DRAM bandwidth remains the same at 320GB/s. This may seem puzzling at first, but even though the serial interface is much more pin efficient than traditional parallel memory interfaces it never hurts to reduce the IO resources even further. With the new faster links number of pins required to achieve the same level of performance is halved, and also reduces the package size if using a 32 lane interface instead of 64. With Avago Technologies 28nm transceivers the power efficiency undoubtedly improves as well.

TSV based DRAM are exactly the kind of technologies needed for the packet buffers of high performance networking systems. The bandwidth and capacity needed to hold the packet while decision processes take place enables designers to take advantage of the high memory transaction rate delivered by the MoSys Bandwidth Engine family.

Bandwidth Engine devices also use a high performance and high efficiency serial interface.
 
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