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Huawei patent reveals 3nm-class process technology plans

Daniel Nenni

Admin
Staff member

  • huawei-patent-reveals-3nm-class-process-technology-plans-—-china-continues-to-move-forward-despite-us-sanctions
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When Huawei and Semiconductor Manufacturing International Co. (SMIC) patented self-aligned quadruple patterning (SAQP) lithography methods to produce advanced microchips earlier this year, most assumed the companies were working on building chips using their 5nm-class fabrication process. Apparently, that’s not the limit of their plans, as Huawei is now looking forward to using quadruple patterning for 3nm-class manufacturing technology as well.

SiCarrier, a state-backed chip manufacturing equipment developer that’s working with Huawei, also patented a multi-patterning technique, confirming SMIC’s plans to use this technology for future nodes. Experts like Dan Hutcheson from TechInsights suggest that while SAQP may allow China to manufacture 5nm-class chips, EUV machines will be essential for long-term competitiveness beyond these nodes. Industry experts never envisioned the use of quadruple patterning for 3nm-class nodes.

7nm-class process technology features 36nm–38nm metal pitches, while 5nm-class nodes shrink the metal pitches to 30nm–32nm. At 3nm, metal pitches will get to approximately 21nm–24nm. That could achieve critical dimensions of approximately 12nm for high-volume manufacturing, something that even Low-NA EUV tools cannot achieve without using of double patterning. Yet it looks like Huawei and SMIC plan to get there with SAQP using DUV tools.

SAQP is crucial for Huawei and SMIC as they lack access to leading-edge lithography tools like ASML’s Twinscan NXT:2100i and Twinscan NXE:3400C/3600D/3800E. That’s due to export rules imposed by the Nerherlands, with the U.S. being the primary instigator of the restrictions. SAQP involves repeatedly etching lines on silicon wafers to increase transistor density, reduce power consumption, and enhance performance. This approach mirrors Intel’s previous attempts to avoid relying on extreme ultraviolet (EUV) lithography machines in 2019–2021 with its 10nm-class (later renamed “Intel 7”) node.

Despite the potential benefits, SAQP’s use presents difficult challenges. Intel’s first-generation 10nm-class process technology failed at least in part due to this method. Yields were rumored to be so bad that the only 10nm Canon Lake CPU only had two CPU cores and the integrated graphics was disabled. However, for SMIC, SAQP is necessary to progress in semiconductor technology, enabling the production of more sophisticated chips — including next-generation HiSilicon Kirin processors for consumer devices and Ascend processors for AI servers.

Although the cost per 5nm or 3nm chip using SAQP will almost certainly be higher, making it less feasible (if at all) for commercial devices, the method remains vital for China’s advancements in semiconductor technology. These advancements are essential not only for consumer electronics but also for applications like supercomputers and potentially for developing military capability.

 
Obviously, this article from Tom's Hardware contains some incorrect information. First, DUV based SAQP (4x) cannot get down to 12nm,but practically around 20nm. It's unclear where this "12nm" comes from, the author may get confused with the previously discussed SASP (6x) patent in our Forum(Semiwiki). The original single-material SAQP process was invented by AMAT engineers back to 2010 but NOT patented, and our industry is using it in FEOL (e.g., fin patterning) for free. The refined multiple-material SAQP process to solve the EPE issue was invented by PKU in 2015 and patented in 2017, and has been extented by TEL and Imec to BEOL (e.g., SAQP based self-aligned block). It remains to be seen how SiCarrier's SAQP (and Intel's introduction of SAQP in 10nm product) can avoid the legal issue of patent infringement. Secondly, the 12nm (metal pitch) process is only available in Huawei's another SASP patent application (WIPO patent application # CN2022/097621: A method of metal integration for fabricating an integrated device). The latest progress of SASP(7x) process development was reported by Westlake University (NOT Huawei) in this year's SPIE Advanced Lithography+Patterning conference though. Currently there is too much misleading information on the web about Huawei's 5-3nm (and beyond) manufacturing.
 
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Obviously, this article from Tom's Hardware contains some incorrect information. First, DUV based SAQP (4x) cannot get down to 12nm,but practically around 20nm.
Maybe it means 12 nm hp instead of pitch? 12 nm pitch is definitely not possible.
 
The original single-material SAQP process was invented by AMAT engineers back to 2010 but NOT patented, and our industry is using it in FEOL (e.g., fin patterning) for free. The refined multiple-material SAQP process to solve the EPE issue was invented by PKU in 2015 and patented in 2017, and has been extented by TEL and Imec to BEOL (e.g., SAQP based self-aligned block). It remains to be seen how SiCarrier's SAQP (and Intel's introduction of SAQP in 10nm product) can avoid the legal issue of patent infringement.
Has the PKU patent licensing been pursued by the school?
 
Maybe it means 12 nm hp instead of pitch? 12 nm pitch is definitely not possible.
I see, you are right, it should mean half pitch. PKU was discussing a legal negotiation with Intel first, but it may not be smooth, not sure what will be coming up eventually. Huawei may want to get around PKU's SAQP patent (US # 9679771 B1) with SiCarrier's new one, but it seems to be difficult as PKU patent was filed in US.
 
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