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How does inter-die connection in MPW compare to integration at PCB/SiP/SoC?

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@@k@sh

New member
As we know MPW is good way to share mask cost for low volume manufacturing. Would like to know how individual blocks of MPW sawed & what is feasibility of using MPW in below situation?
Consider situation where same designer has multiple (say 2) independent design blocks (both needing same process technology) where for main target application first block output directly act as input to second block.

[Option1] Single mask SoC with both blocks tightly packed.
{pro} Perfect for main target application which requires both blocks
{con} Over-spec for applications which require only one of it.

[Option2] Still single mask with output pads of first shorted to input pads of second block so as to use act as SoC; but with enough spacing to saw through it if needed.
{con} Silicon area overhead/wastage for main application requiring both blocks. But still less overhead compared to SiP
{con} High loading at interface for driving long connections. How does this loading due to interconnection at lower metal layers compare to loading due to interconnection required for SiP or multi-D ICs?
{pro} Perfect for secondary applications which need only one of it. Can use it as 2 different products by sawing it separately.
{pro} Better yield as failure of one block still allows to use other. Good die of one block and good die of other block can be integrated as SiP or as 2 packages at PCB board level

@admin, no separate forum category for supporting industries group of wafer/process/testing equipment suppliers, testing/packaging services?
 
I don't think your option 2 would work. The passivation would be a problem for sure if you want to optionally saw through the two parts (although what you do with the second one if there is only demand for the first is a challenge). Plus I'm not sure what happens to the signal lines you just cut through, they have optional pads or what?

This reminds me of a guy I sat next to on a plane back in the days of Gene Amdahl's Trilogy wafer scale integration (back when a wafer was just 5"). He worked for Digital and though they could put lots of microVax chips with some memory on a single wafer and connect them through on-chip ethernet. Instead of requiring the esoteric technology Trilogy needed to get signals in and out of the chip, there would only be a need for power, ground, and ethernet.
 
Paul McLellan said:
(although what you do with the second one if there is only demand for the first is a challenge). Plus I'm not sure what happens to the signal lines you just cut through, they have optional pads or what?
Click to expand...
OK to be more specific first & second is exact copy, just want to keep option to sell it as single-core processor for low complex application & multi-core solution for high complexity application w/o another TO
Consider it as SPW where every small core has it's own pad frame to act as independent die. Just using that scribe lines area to create connections to make it multi-core
 
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