How are the benefits of BSPD affected by 3D stacking?

[mattyenright]

Like I said, how big a problem this is depends on the chip design. There's a fundamental thermal problem with BSPD if you have small circuits on-chip with high power density, I gave a couple of examples. If you can spread out/distribute the "hot bits" (or keep the heatsink cooler) then BSPD is less of a problem, you just end up with all the transistors running a bit hotter.

There's no "magic sauce" here, it's basic physics -- thin/narrow metal layers with tiny vias all surrounded by dielectric on the frontside are lousy at heat conduction, both vertical and lateral. If you try and put in big slabs of metal/multiple via pillars on the frontside to help then you've just reintroduced what you tried to get rid of by moving power distribution to the backside, the density goes back down and you've lost one of the big advantages of BSPD (moving all this heavy metal to underneath the transistors).

Maybe this is OK for Intel with relatively low clock rates (*only* 6GHz!) and large functional blocks. It's definitely not OK at 10x the clock rate... :-(

Like I said, this is based on actual circuit thermal simulations, not marketing handwaving and Powerpoint publicity slides... ;-)

That does not sound good for 3D stacked transistors……. Unless they run at the super high speed of 100mhz.

 

[IanD]

BSPD is garbage... It's a pity
With this, Intel's process will also be a piece of crap

Nope, that's not true. For chips whose design suits BSPD -- for example GPU/AI chips for HPC, which is a huge and rapidly expanding part if the market -- it's great, better power distribution, better PPA. TSMCs recommendation that it's best suited for actively-cooled HPC devices with dense power grids sums it up perfectly.

Which is why TSMC have both BSPD and FSPD versions of their processes on the roadmap for at least the next couple of nodes, because they suit different applications. And why Intel Foundry going BSPD-only is going to severely reduce their potential customer base -- this is understandable because Intel are still CPU-obsessed, but I don't think it's a good decision if they want to be a successful foundry.

 

[IanD]

After all, the company Intel is not decent, it is not decent to have such a defective technology as a standard equipment, which cannot be said to be a next-generation new technology full of flaws.
It's a Naturally failure Please don't stand up again...

It's not defective, it's excellent for the right applications -- but not best suited for a lot of others.

 

[IanD]

That does not sound good for 3D stacked transistors……. Unless they run at the super high speed of 100mhz.

They're probably not that much worse than nanosheet devices, which are already worse then FinFETs for self-heating because they have poorer thermal contact to the substrate -- we see worse SHE in N2 (nanosheet) than N3 FinFET) because of this.

This causes hotspots at the level of individual transistor gates, which can easily run 20C hotter than the substrate temperature.

The problem with BSPD is at the next level up, especially in high-power circuits made up of many individual transistors or parallel gates where they all heat each other up but the heat can't escape easily. You can try and reduce this by spreading all the "hot" gates out using dummy gates between them, but then the interconnect capacitance/resistance goes up so the circuit slows down and dissipates more power, so you have to make the transistors bigger, which adds more capacitance, which puts the power up more... :-(

If the device doesn't have this problem or can be redesigned to avoid it (not always possible) then BSPD is great, especially if you have a heavy/dense power grid moving to the backside so get a big area reduction.

But in many cases (e.g. less dense power grid) the area/power savings are reduced, and the die cost is higher (BSPD wafer cost is currently considerably higher than FSPD) -- and if self-heating is a big issue BSPD is a no-no.

Horses for courses... ;-)

 

[benb]

If there were a way to do BSPD without thinning the Si substrate would that solve the heat spreading problem? All that’s needed is 700um etches…or whatever the thickness is that’s needed to dissipate the heat.

 

[IanD]

If there were a way to do BSPD without thinning the Si substrate would that solve the heat spreading problem? All that’s needed is 700um etches…or whatever the thickness is that’s needed to dissipate the heat.

Doesn't work. The substrate has to be thin because the vias connecting to the transistor source/drains are very small and so have to be very short. And the problem is that the (thermally conductive) silicon substrate is now on the "wrong side" of the transistors -- instead of being between them and the heatsink/lid (above the die for a face-down flip-chip) it's not between them and the I/O balls/pads/socket (underneath the die), the opposite side to the package lid/heatsink.

 

[IanD]

BSPDN is trash right...
I don't understand why this technology is being lifted so far
This technology has no value

<sigh> no it's not "trash", it's a very good technology for the right applications -- including AI/HPC, which will soon be the biggest one if trends continue.

It's just not a magic bullet for *all* applications, for many good old FSPD is better.

Please stop repeatedly making Intel-bashing posts about a subject you clearly don't understand and which are simply incorrect... ;-)

 

[tomatoma]

Doesn't work. The substrate has to be thin because the vias connecting to the transistor source/drains are very small and so have to be very short. And the problem is that the (thermally conductive) silicon substrate is now on the "wrong side" of the transistors -- instead of being between them and the heatsink/lid (above the die for a face-down flip-chip) it's not between them and the I/O balls/pads/socket (underneath the die), the opposite side to the package lid/heatsink.

Please wait
If you use BSPDN, for example, in terms of LGA sockets, a die will be mounted on the contact pin side of the LGA! ?
How do you cool it in this case?
If that's true, Intel is lying about Panther Lake

 

[IanD]

Please wait
If you use BSPDN, for example, in terms of LGA sockets, a die will be mounted on the contact pin side of the LGA! ?
How do you cool it in this case?
If that's true, Intel could be lying in Panther Lake

No; the vertical order of layers in a packaged chip is as follows:

FSPD (conventional, die face down)
1. heatsink (top)
2. TIM
3. thick silicon substrate (e.g. 700um) -- high thermal conductivity
4. transistors -- hot!!!
5. thin/fine pitch metal + low-k dielectrics -- low thermal conductivity
6. thick/coarse pitch metal + oxide dielectric
7. solder bumps/copper pillars
8. package substrate
9. BGA solder balls/LGA pads
10. socket
11. PCB (bottom)

BSPD (die face up, ultra-thin substrate with TSVs)
1. heatsink (top)
2. TIM
3. thin/fine pitch metal + low-k dielectrics -- low thermal conductivity
4. transistors -- hot!!!
5. ultra-thin silicon substrate (e.g. <1um) with TSVs
6. thick/coarse pitch metal + oxide dielectric
7. solder bumps/copper pillars
8. package substrate
9. BGA solder balls/LGA pads
10. socket
11. PCB (bottom)

 

[siliconbruh999]

@IanD what happens to a BSPDN Chip for example an Intel 18A CPU running 6+ GHz do you think traditional cooling will be able to dissipate it. I am talking about copper heatsink and Water-cooled AIO not LN2.

 

[IanD]

@IanD what happens to a BSPDN Chip for example an Intel 18A CPU running 6+ GHz do you think traditional cooling will be able to dissipate it. I am talking about copper heatsink and Water-cooled AIO not LN2.

Like I said, AI/HPC/GPU/CPU are applications for which BSPD is suitable (and targeted at), given a decent heatsink -- meaning not LN2, which is not recommended by CPU manufacturers!

I'm sure Intel have thought of this, after all it's their CPU and process -- though their recent CPUs have not exactly been notable for running cool, especially at high core clock rates...