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High NA EUV Equipment is Bound to be a Burden for Chipmakers

Daniel Nenni

Admin
Staff member
EUV process 'fades out' in next-generation memory, foundries use it from '1.4nm'

Samsung Electronics and SK Hynix are moving to postpone the introduction of ASML's 'high numerical aperture (NA) extreme ultraviolet (EUV)' equipment for the DRAM exposure process. This is due to the astronomical price of the equipment and the expected changes in the DRAM structure in the future.

Samsung Electronics and SK Hynix are planning to mass produce 3D DRAMs after 2030. They plan to use argon fluoride (ArF) equipment, not EUV equipment, for the 3D DRAM exposure process. For this reason, the introduction of high NA EUV equipment is bound to be a burden for chipmakers.

Next-generation memory '3D DRAM' not utilizing EUV process

According to the industry on the 15th, Samsung Electronics will preemptively apply high NA EUV equipment to its foundry. It is reported that they are considering whether to apply it to the 10nm 7th generation DRAM (1d DRAM) in the DRAM process or to mass production of vertical channel transistor (VCT) DRAMs. The reason

memory companies are taking a conservative stance on the introduction of high NA EUV is due to the future DRAM roadmap. According to the DRAM roadmap of Samsung Electronics and SK Hynix, the memory architecture will change in the order of 6F square DRAM → 4F square DRAM → 3D DRAM.

Among these, the 3D DRAM exposure process does not require the use of high NA EUV equipment or low NA EUV equipment. 3D DRAM is a memory concept that vertically stacks DRAM cells like NAND. While existing DRAMs have increased transistors through fine processes, 3D DRAM expands transistors through vertical stacking. Therefore, ArF equipment, not EUV equipment, is used for the exposure process.

20250515100814384_n.png

ASML's high-NA EUV equipment. Photo: ASML

This means that even if the latest equipment worth over 500 billion won is introduced, the time that it can be used for cutting-edge DRAM mass production will not be long. However, the 4F Square DRAM that both companies plan to mass-produce in the late 2020s is likely to use high-NA EUV equipment. Samsung Electronics calls it VCT DRAM and SK Hynix calls it vertical gate (VG) DRAM, which requires an EUV process for mass production of this memory.

SK Hynix is taking a similar stance to Samsung Electronics on the introduction of high-NA EUV. In particular, it has been understood that SK Hynix is reviewing the introduction of equipment more carefully than Samsung Electronics since it must use high-NA EUV equipment only for the memory process.

An official familiar with Samsung Electronics' next-generation DRAM development issues explained, "I understand that Samsung Electronics has postponed the completion date of 3D DRAM development from the original 2030 to 2032~2033," adding, "Since 3D DRAM has a completely new structure, the related ecosystem has not been established yet." He added, "The existing vertical deposition and etching need to be converted to horizontal, but this technological difficulty is considerable." "The materials have isotropic properties, so it is not easy to control."

High-NA EUV equipment, targeting application to '1.4nm' in foundries

High-NA EUV equipment will be utilized first in the foundry process. However, it is expected to take some time until high-NA EUV is applied to mass production. ASML predicted that high-NA EUV equipment will be applied to mass production processes after 2027.

Currently, the three foundries that have received high-NA EUV equipment from ASML are Intel, TSMC, and Samsung Electronics. All of this equipment is for R&D, not mass production.

It has been confirmed that Samsung Electronics is developing the process assuming that high-NA EUV equipment will be used in the foundry 1.4nm process. Samsung Electronics is aiming for mass production of the 1.4nm process in 2027. Accordingly, the high NA EUV equipment 'EXE:5000' that Samsung Electronics is currently setting up at NRD-K will also be used primarily for R&D purposes.

TSMC is delaying the use of the high NA EUV equipment as much as possible. At a recent event, it was announced that the plan is to use the high NA EUV equipment starting from the derivative process A14P, not A14 (1.4 nm). This is not unrelated to the price of the high NA EUV equipment.

 
Among these, the 3D DRAM exposure process does not require the use of high NA EUV equipment or low NA EUV equipment. 3D DRAM is a memory concept that vertically stacks DRAM cells like NAND. While existing DRAMs have increased transistors through fine processes, 3D DRAM expands transistors through vertical stacking. Therefore, ArF equipment, not EUV equipment, is used for the exposure process.
At least for memory. Logic, maybe not so much. But it does mean that logic has to carry the cost burden of development and lower volumes - not amortized over memory.
 
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At least for memory. Logic, maybe not so much. But it does mean that logic has to carry to the cost burden of development and lower volumes - not amortized over memory.

I believe Intel Foundry and Samsung will follow TSMC into NHA EUV. TSMC has such a strong pull with customers and the ecosystem Intel and Samsung would be foolish to try and swim against it. My opinion.
 
I said last week that HighNA will not win the foundry war. Still true

Now i would say implementation too early could be a friendly fire casualty to the foundry that tries it.

Remember when people said Intel was so smart to order HighNA tools before TSMC? Perhaps we should wait and see how the story ends.
maybe not now but in few years i can definitely see an impact like EUV had only for logic though.
 
Agreed, but being first to HNA-EUV will not get you anywhere. And thinking you know more about EUV than TSMC is a step backwards.
Intel may not know as much as about Low NA EUV as TSMC but for high-Na they have the most experience.I think they are not confident enough with High-Na that is why there is a 14A without High-Na. Getting experience with high-NA is also a good thing and may help out in future but not now.
 
Intel may not know as much as about Low NA EUV as TSMC but for high-Na they have the most experience.I think they are not confident enough with High-Na that is why there is a 14A without High-Na. Getting experience with high-NA is also a good thing and may help out in future but not now.

I think Pat G was confident enough with HNA-EUV to put it into production last year. :ROFLMAO: Remember, these systems cost $380M each and you will need a dozen of them per fab for full HNA-EUV? That is a big expense for a new foundry that is trying to break even in 2027.

My prediction is that Intel will follow the TSMC N7, N7+, N6 strategy by getting 14A into HVM then introducing 2-3 layers with 14A+and moving to full HNA-EUV (12 layers?) at the next node.
 
High-NA adds 3 new problems Low-NA doesn't have: (1) reduced depth of focus (so need much thinner resist films); (2) the 104 mm x 132 mm mask area maps to a 26 mm x 16.5 mm wafer exposure field instead of the conventional 26 mm x 33 mm; (3) central obscuration will limit some combinations of dense line pitches and staggered 2D pitches.

It also continues/exacerbates a problem that low-NA already has, stochastics. This was already a problem observed at 48 nm pitch.

Finally there is the issue of electron blur, which makes the wavelength/NA reduction practically meaningless.
 
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