Guidelines on bond pad driver die area?

[jms_embedded]

Are there any guidelines on how large is required for the driver circuitry for input / output / power pads? If I am looking at a photomicrograph, I can see the bond pad area pretty easily. Is there a way to determine roughly how much additional silicon area is required to support that pad? (1% of pad area? 10%? 100%?)

I am trying to get a sense of how much of an IC's area doesn't benefit from die shrink. (assuming the functionality is fixed + the number of transistors is the same.)

For example the pads on the left/bottom sides of the 6502 (http://www.visual6502.org/images/6502/6502_top_op10x_BF_4677.png) have what look like relatively large transistors next to them, compared to the others throughout the chip, and I'd guess those are the driver transistors. But I'm not sure how it works with submicron geometry processes.

 

[IanD]

Nothing in this image shows transistors, unless you have a corresponding poly-level image that isn't included. You're looking exclusively at the top metal layer (which looks to be Al) and I can see 1-2 Cu layers routed under that, but nothing at the poly level. The interleaved metal bars next to the pads are likely metal-finger capacitors, and those will size based on the signal swing (frequency, attenuation) you need the bump to have (coupled with the resistive load of the wire bond between the Si pad and the package pad).

The "interleaved metal bars" are the driver output transistors, nothing to do with metal-finger capacitors or signal swing or wire bond resistance...