Everything that you need to know about reset system design but probably dont

[jt_eaton]

<style type="text/css">P { margin-bottom: 0.08in; }</style> After almost 30 years as a product and IC designer I am still amused when I find two designers arguing over what type of reset system to design. These usually start off civil enough but quickly devolve into both sides flinging factoids,folklore and fiction back and forth hoping something will stick. It never does and we continue to repeat this farce over and over. I have even seen engineers support one side or the other because they “feel” that it is better. When engineers start talking about feelings then you know that we are in a mess.

So I thought I would write this essay how things should work and explain why we still continue to argue over what should be a simple straight forward system.

If you ask both sides to describe what the mission statement for the reset system is then you will usually find that they are in agreement. "The reset system forces all nodes in the system into a known

good start state while the reset button is pressed". From there they diverge on how to do it.

So who is responsible for the reset system's mission statement? It comes like all IC requirements from the product development team. This team does a make/buy analysis and decides to create an IC. A requirements doc is created that lists all signals connected to the chip along with all the mission statements for the entire chip.

Somebody on the product team will be responsible for the reset design. They will spec how it is created,filtered and distributed to all chips. The reset system mission statement comes from this person.

And this is the crux of our problem. I have a desktop pc, tablet , dsl modem,firewall and hotspot and they all reset the same way. In fact all products behave the same during reset. You press a button and after some time lag the product returns to its reset state. The time lag can range from fractions of a second up to 10 or 20 seconds.

When an IC designer designs a reset system they will always try to reset everything as soon as possible. If you even suggest that maybe you could wait 10 ns for the next clock edge before applying the reset then the asynchronous reset crowd will scream that is cannot be done and it must be reset NOW!!!.

They do this because their mission statement's only focus is what happens when the button is pressed. It doesn't say anything about waiting. Product designers could care less. Go ahead and wait billions of nanoseconds. No problem.

Product designers are using a different mission statement for reset than IC designers. Their mission statement is “If the reset button is not pressed then do nothing, otherwise wait long enough to be absolutely sure that the button is pressed before forcing all nodes in the system into a known good start state”.

They reason they do this is because the biggest threat to a products reset system is Electrostatic Discharge (ESD). If a product can see spurious resets from esd events in the field then it is doomed. Delaying reset until you are certain will prevent these failures. It is a nuisance but still quite acceptable to the customer.

The product reset designer must create a Low Pass Filter that will pass the valid reset while blocking any and all noise. One of the side effects of a low pass filter is that you will always insert a delay after the button press before the system can respond. Reset filters need to be under 100 hz so those delays can be in the milliseconds.

So our product designer has two choices for designing the filter. They can use analog components or they can use digital. Analog is nice because it is completely asynchronous and works even if your clock circuit fails to start. This is essential in embedded systems that drive actuators.

Digital on the other hand is cheap. The cost of putting a digital filter on the reset signal is zero. The number of gates is a round off error of a round off error. It also has zero impact on the PC board layout.
Analog filters use capacitors and the lower the frequency the larger the capacitor. In the mobile arena this is a huge cost.

So what is the best solution? Use both. Put in a analog low pass filter with a high cutoff frequency to keep the component size small. This will let you control the pads if your clock source fails to startup. Then feed this signal into a digital low pass filter to do the heavy lifting and give you the millisecond to multisecond delays that you need. Nice, simple ,eloquent and cost effective.

But there is a problem. There is one side in the reset debate that insists on designing ICs with a combinational path from the reset input pad to EVERY flip-flop and latch in the chip. They do this because they want to be sure that when reset is asserted that the IC will respond.

The problem is that if you want to use a digital low pass filter then it has to be able to block this path and prevent the signal on the reset pad from reseting any flip-flops. You can't do both.

You cannot use a digital filter to block noise on reset because an asychronous reset system will bypass the filter and send the noise pulse to the entire design.

I have noticed that most reset discussions are only among IC designers and rarely is this issued discussed with the product teams. This is like having IC designers chose a microprocessor without ever talking to any firmware engineers.

So how did we get into this mess? IC designers did not take their reset mission statement from the product teams, they up made their own that made it easier to design the IC at the expense of the product performance. This is voodoo engineering at its worst.

There are some good reasons for using an asynchronous reset system.It turns out that there are only five ways that you can screw up your reset system design.

1) Fail to connect flip-flop to reset system. Reset assertion never makes it to the flip-flip.

2) Fail to connect reset deassertion to a flip-flop. The reset assertion makes it so it can reset but is locked in that state forever.

3) Pick a wrong reset value.

4) Fail to reset combinatorial loops. We reset the design by resetting all the flip-flops. Loops do not have flip-flop drivers so we have to add an asynchronous reset.

5) Noise or ESD


The reason that the asynchronous wackos want to use their solution is failure #1. If I insist that all my IP has 100% asynchronous resets then it is very easy to verify that all IP is in compliance and that I will have no failures because some flip-flop was left out of the reset system. Its actually a good idea and 40 years ago it was the way that all systems were designed.

The problem we have today is that choosing the asynchronous option makes it easier to design the IC but harder to design the product. This is not a decision that an IC design team can make on their own, it has to come down from the product design team. Remember, the IC team is working for the Product team. They are the ones that have to make this decision.

If you take a design inserted with any of the first four reset failures then I can give you a simulation or spyglass rule or some other rtl checker that will read your design and catch that error. There is no tool
in the digital toolbox that can catch an esd failure error. Designing a working reset system is not as much of a design problem as it is a verification problem. Asynchronous resets do make it easier but at a significant cost to the product.

No modern IC design team should be using asynchronous resets inside the core of todays designs. You will still need them in the pad_ring but never in the core. Any IC team still using asynchronous resets should get rid of them. You will need to improve your verification effort to make up for the harder task of verifying synchronous resets but that is what you are being paid to do.

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[Daniel Payne]

Thanks for raising the issue of synchronous versus asynchronous reset for an IC and an electronic system. Which approach is being taught at Universities, popular books and training classes?

 

[Kinnerk]

Good article. A little biased if I were to be honest, but interesting nevertheless.

IC engineers that prefer the use of asynchronous resets are far from being wackos, the benefits for so doing are both tangible and well documented c.f. http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf. I can't improve on the paper but note the disadvantages associated with synchronous resets for...

1. Gate-level simulations
2. Gated clocks

Those being 2 critical components of the majority of modern design flows. The advantages of asynchronous resets, as you pointed out, must be traded off against the ESD/noise failure mechanisms at the Product level but it should be noted that using synchronous resets comes with it's own set of problems.

 

[jt_eaton]

Good article. A little biased if I were to be honest, but interesting nevertheless.

IC engineers that prefer the use of asynchronous resets are far from being wackos, the benefits for so doing are both tangible and well documented c.f. http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf. I can't improve on the paper but note the disadvantages associated with synchronous resets for...

1. Gate-level simulations
2. Gated clocks

Those being 2 critical components of the majority of modern design flows. The advantages of asynchronous resets, as you pointed out, must be traded off against the ESD/noise failure mechanisms at the Product level but it should be noted that using synchronous resets comes with it's own set of problems.

Back annotated gate level simulations are a wonderful tool for verifying any ip that has both a clock and a reset input. The problem is that the reset system does not have a reset input and so has to be designed to self start from all possible power up states. The clock system is the same way because it has to be running during the time that the power_on reset pin is asserted. Your simulation and test engineers will need to reset both of them and they will have some means to do so that is not driven from the power_on reset pin.

The reason some designers have a problem running gate sims on a synchronous reset system is that simulators are not capable of handling a design once it contains X's. They are trying to use a simulator in a manner that was never intended to work. That is a tool usage problem. By the same token you cannot run back annotated gate sims on a design that has asynchronous signals crossing clock domains. But we do that all the time and it works fine. The clock crossing engineers tend to be real engineers (as opposed to wackos) who understand their tools so they came up with a process that works around verilogs limitations.

Here is how you run gate sims on a synchronous reset design.

1) Every flip-flop in the design must be on the reset system. The rtl should be coded so that the reset is the first priority to prevent X-unknowns from generating a false reset value.

2) The test suite should verify that all flip-flops are reset at power up

3) Use LEC to verify that the gates logic matches the rtl coding.

4) Call it good. When you run gate sims you use a flip-flop model that initilizes to either a 1 or a 0. It doesn't matter as long as it is not X. You won't be testing the reset system but thats OK because you have already veriified it. You will be able to test the rest of the design.

The gated clocks issue occurs with both synchronous and asynchronous resets. Your deasserting edge must coincide with the target flip-flops clocking edge. If the target flip-flop is clock gated then the reset source for that flip-flop must also use the same clock gating. This is true for both synchronous and asynchronous resets. The only thing special about synchronous reset is that you do have to enable the clock long enough to set your default state.

The main point of my essay is the all the advantages of asynchronous reset simple help the IC designer verify the design while the advantages of synchronous translate into features that help the Customer. Anytime an engineer decides that the best solution for the customer happens to be the one that is easiest for them to implement then somebody needs to start asking some hard questions.

 

[JohanDijkhuis]

Mixed signal chips will need an asynchronous reset (probably similar as the pad-ring). The inputs to analog must be in reset state (usually all zero) during start-up otherwise high power circuits can either prevent proper start-up or self-destruct (e.g. too high voltage from programmable LDO).