DVCon 2012 Trip Reports (Free iPad2)

[Daniel Nenni]

The Design & Verification Conference & Exhibition is the premier conference for functional design and verification, focused on bringing information from the leading edge of technology, techniques, standards and methods.

“If you are not facing verification challenges you are not doing verification!”

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DVCon: Hardware/software Co-design from a Software Perspective

DVCon: Formal Verification with lunch

Using "Apps" to Take Formal Analysis Mainstream

Design & Verification of Platform-Based, Multi-Core SoCs

Free “Power” Lunch at DVCon Exposes Verification Challenges

DVCon 2012–better than ever, starts on Monday, Feb 27

Synopsys at DVCon: tutorial, lunch, keynote, exhibits and more

UVM: Some Thoughts Before DVCon

DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards
[h=2]DVCon User Panelists: Is Low Power Design Worth the Costs?[/h]

DVCon Panel: Will Differentiation Through Software Kill Chip Design?

DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?


Access to DVCon Papers!


Take the DVCon Conference Survey here!

Post a trip report here and you may win an iPad2. Someone will win one so it might as well be you!

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Warning: iPad2s can be addictive, mine is next to my bed and it gets more attention than my wife. I now also own (6) iPhone 4s’s so IOS is also contagious!

If you are at DVCon 2012 it would be a pleasure to meet you. Paul McLellan and I will be there wandering the sessions, halls, free lunches, and hosted bars.

Cheers!

D.A.N.

 

[Paul McLellan]

At DVCon earlier this week, I was the moderator on a panel on hardware/software co-design. The panel was sponsored by the EDAC small and emerging companies committee. Despite most of the people in the room being semiconductor design and verification engineers, we focused mostly on the software issue. Namely, how do we develop software in parallel with the hardware.


The panellists were:

• Atul Kwatra of Intel
• Michael James of Lockheed-Martin Space Systems
• Bill Neifert of Carbon Design Systems (holding the flag for actual small EDA companies, although whether emerging is a good adjective after 10 years is an exercise for the reader

The fourth panelist, Don Williiams from Cisco and then Skype, was unfortunately sick and unable to attend.


Most of the discussion centered around virtual platform technology of one sort or another. Intel acquired, through its Wind River subsidiary, Virtutech (where I used to work). Michael James used to work with me at Virtutech and, at Lockheed, is a big user of its technology Simics. And Carbon is a company that today mainly sells virtual platform simulation and modeling technology. Interestingly, in Aart's keynote later in the week he also spent some time talking about virtual platform technology. Synopsys acquired 3 virtual platform companies (Virtio, VaST and CoWare) and has been merging the technologies. They have also been pushing to solve the model availability problem by creating a focus for System-C transactional level models TLMCentral.


Intel uses this technology at various levels from doing software development to invstigating power and thermal issues in chips. As everyone knows, Intel is increasingly trying to grow a business around SoCs incorporating Atom, most notably in the communication area where at the Mobile World Congress this week in Barcelona they laid out more of their roadmap.


Satellites have some unique issues. You don't build very many of them and they are very expensive. Plus you can't make service calls so everything that might go wrong has to be tested in advance. However, you can't actually break them to check this out. So in this environment virtual platforms are perfect. Since the processors on satellites are rad-hard they run very slowly, so virtual platforms can even be faster than the real hardware.


Carbon doesn't do embedded software development themselves, but their customers do. They use Carbon's virtual platform technology for a wide range of applications from 8-bit processors running in toasters up to 64-bit multi-core applications.


The discussion lasted for over an hour and a half and the questions just kept coming. So much so that I never needed to get to the questions I'd prepared earlier in case the audience was small or unwilling to ask questions. In fact the audience was large, with over 80 people attending, and not the slightest bit hesitant to ask questions.

Memo to panel session organizers: feed the audience free beer before the panel session starts, it makes for a more lively discussion.

 

[Paul McLellan]

Nothing really directly to do with DVCon, but up the road at Silicon Valley Bank on the Wednesday evening of DVCon was the EDAC CEO Forecast meeting.

This year's CEO forecast panel was held at Silicon Valley Bank. Bankers live better than verification engineers, as if you didn't know, based on the quality of the wine they were serving compared to DVCon.

This year the panelists were Ed Cheng from Gradient, Lip-Bu, Aart and Wally (and if you don't know who they are you haven't been paying attention) and Simon Segars of ARM (not their CEO, of course). Ed Sperling moderated. Somebody had managed to dig up the fact that at the start of his career he'd been a crime reporter, so that made sure that we only got truthful answers all evening!

I've reported on it here.

 

[Paul McLellan]

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Jasper sponsored a lunch (deconstructed salad nicoise was something I've not seen before) on, surprise, formal verification.

They had 3 customers:
Jon Michelson of NVIDIA
Alan Hunter of ARM
Ambar Sarkar of Paradigm Works
and the discussion was moderated by Rajeev Ranjan, Jasper's CTO.

The first thing I discovered was that formal verification specialists must have really good eyesight, because apart from Alan Hunter, everyone's slides were in tiny print completely impossible to read. And I wasn't even at the back of the room.

Everyone started by talking a little about how they used formal verification.

ARM builds a lot of "test chips" for their IP to make sure it all operates correctly together. I put test chips in quotes since they don't actually fabricate the chips, which would be a huge investment, they just verify everything about them. Formal verification is great for checking that everything is correctly put together, especially memory maps. They also used it to validate the ACE protocol (which they talked about at the Jasper User Group Meeting and I blogged on here). They have tried to use Japer on Cortex A15 but the number of constraints and its size is a challenge. But formal verification is very much part of the verification flow, but in some design centers more than others.

Ambar talked about coverage-driven verification. One point he made was that just writing down formal properties that a design is meant to have helps a lot, even if some of the properties cannot be completely verified.

Jon, who only recently joined NVIDIA, talked about SFV: Semi-Formal Verification. They prioritize to focus on the top N units per chips based on complexity, criticality and the number of ECOs found in that part of the chip last time (note that this is ECOs, bugs that escaped the first time around, not simply bugs that were found during development). Another prime use is with simulation coverage, where formal verification can quickly decide which code is actually unreachable (so can be ignored) and which is reachable and so needs to be tested.

Some random notes from the rest of the lunch:

Formal verification is a huge increase in productivity for connectivity checking. Even something as basic as making sure the I/Os are hooked up correctly.

NVIDIA have chips that they are shipping that were supposed to be bug free but when run through formal have stuff lurking in obscure corners (which, of course, is something that formal is so good at discovering).

Alan said that it has been an uphill struggle to introduce formal into ARM. Still patchy.

Formal verification is a competitive advantage. It helps you get to tapeout faster.

People are skeptical about a "lint" for formal friendly RTL. Of course the people writing it tend to optimize it for implementation but if it gets too deep it can be very time consuming to verify. But formal tools seem to improve as fast as anyone can write lint tools so it is a moving target.

Engineers who only use formal occasionally (work in a small company doing a single design each year, say) can use formal effectively. The biggest problem is design understanding. Plus when you come back to formal after 8 months off, you get surprised by how much more powerful it has become.

 

[Daniel Nenni]

The 20[SUP]th[/SUP] annual Design and Verification Conference (DVCon) wrapped up this week with continued growth in attendance and much enthusiasm from attendees. Overall attendance rose almost 10% to 834. Exhibits were sold out again this year with 35 exhibitors, 8 of them for the first time.

This year's DVCon was much like last year only more people. I like DVCon since it is very focused, with a great location, and much less sales and marketing theatrics than most conferences. I'm not a verification person per say but I do know how to spell Calibre. I also worked with DRC start-up Polyteda for a year or so, which felt like a lifetime! This was at 40nm and I can only imagine what new verification horrors are lurking at 28nm and below. I can tell you one thing, I will NEVER EVER work for another DRC start-up unless they have $100M+ in the bank.

The Award for Best Paper, as voted by conference attendees, went to Erik Seligman, Dmitry Korchemny and Laurence Bisht, Intel Corp. for their paper, “SystemVerilog Assertion Linting: Closing Potentially Critical Verification Holes.” Second prize went to Rich Edelman, Raghu Ardeishar and John Amouroux, Mentor Graphics Corp. for “Better Living Through Better Class-Based SystemVerilog Debug.”

I had meetings scheduled back-to-back for most of the time so I did not attend papers or keynotes. For me, talking to people in the halls is the best place to collect data. I also saw lots of friends and co-workers from my 28+ years in the semiconductor ecosystem. Okay. now I feel old.

Two honorable mentions were awarded: “Yikes! Why is My SystemVerilog Testbench so Slow?” by Frank Kampf, IBM Corp. and Justin Sprague and Adam Sherer, Cadence Design Systems, Inc. and “Keeping Up with Chip - The Proposed SystemVerilog 2012 Standard Makes Verifying Ever-Increasing Design Complexity More Efficient” by Stuart Sutherland, Sutherland Hdl, Inc. and Tom Fitzpatrick, Mentor Graphics Corp.

This is the Semiconductor Wiki Project not the Semiconductor Wiki Leak Project but people still like to tell me secrets, rumors, and funny stories that mostly I cannot post.

“There was definitely a buzz coming into DVCon this year,” commented Karen Bartleson, DVCon General Chair. “I think attendees came in with high expectations and left feeling very satisfied. Our Technical Program Committee had outstanding submissions to choose from this year and they were able to expand the program to offer even more valuable content. There was also a lot of sharing of ideas and networking during the breaks, which has become a traditional and anticipated part of DVCon.”

Next week I will be at DATE in Dresden mostly because I have never been to Dresden. I'm also looking forward to touring the GlobalFoundries Fab and spending time with the GFI guys. Lots to be learned there. Plus I love German food and German women (my wife does not read my forum posts).

DVCon General Chair for 2013 will be Stan Krolikoski, Ph.D. He was previously the Tutorial and Panel Chair. Sarkar will continue as the Program Chair. The poster sessions have become a mainstay of DVCon. This year attendees were crowded around the presentations, getting an up close opportunity for information gathering.

People are still talking about the Magma acquisition. I'm telling you, it is a great thing for EDA. The only challenege will be keeping Synopsys humble but that will be up to you customers. Please keep investing in emerging technology, emerging companies, and keep doing joint development activities with us. When I first started in EDA in 1984 vendors knew much more about semiconductor design and manufacturing than the fabless companies. Today that is not the case, not by a long shot, so it is up to you customers to educate us and keep EDA on the right track.

Other highlights of the week included the panel, “Build or buy: Which is the Best Practice for Hardware-Assisted Verification?” moderated by Brian Bailey. The Industry Leaders Panel, “The Resurgence of Chip Design,” moderated by JL Gray, gave attendees a lot to ponder as the luminaries discussed how the need for increased collaboration between hardware and software teams is critical to the continued resurgence of chip design.

I met a couple of new companies which were very interesting. Missing Link Tools was my favorite, and not just because of the name and logo. They do something that I have not seen done before and the guys were fun to talk with, very passionate about what they are doing.
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About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. For more information about DVCon, please visit www.dvcon.org. Follow @dvcon on Twitter or to comment, please use #dvcon.

 

[admin]

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Dan and Paul did great reports so both will get new iPads! Congrats to Dan and Paul and thank you for bringing DVCon 2012 to SemiWiki!