Decentralised Clocking Mechanism?

[alexberka]

Groups of musicians are generally synchronised by taking the lead from the beat established by one member, who serves as a master clock generator, for example an orchestra’s conductor or a rock band’s drummer. But this study Optimal feedback correction in string quartet synchronization establishes that a string quartet sometimes has no leader, where each player continuously modifies their tempo to match that of the other three players. Could this somehow be the basis for a decentralized clocking mechanism, enabling a larger synchronised chip area than conventional H-tree based master clock?

 

[Daniel Payne]

Most digital SoCs have synchronous clocking methodologies, then add multiple clock domains to help control power, however each clock domain is typically in-phase with a global clock.

There are self-clocked methodologies out there: https://www.semiwiki.com/forum/content/2381-ic-design-no-clocksq-used-smart-card.html

 

[Staf_Verhaegen]

Could this somehow be the basis for a decentralized clocking mechanism, enabling a larger synchronised chip area than conventional H-tree based master clock?

I don't see the problem, distributing a clock in a H-tree is known and I don't think there are showstoppers; problem is not being able to get the skew low enough but the power consumption of the clock tree. As Daniel also mentioned the way to avoid that is using self timed (or asynchronous) logic but there the synthesis flow is not mature. Also as Daniel said the reason you have different clock domains is not because of difficulty in distributing a synchornized clock but because you want to be able to run different parts of the chip at different clock speeds for power reasons. These domains are thus non-synchronized by definition.

 

[alexberka]

Thanks for the link Daniel, I am very interested in comparing the differing tradeoffs associated with synchronous and asynchronous logic. I guess I should rephrase the question, might there be better ways (eg more power efficient) of achieving the global synchronisation required to keep multiple clock domains in phase, instead of the H-tree? Or perhaps there are not enough domains to make the power dissipation of the H-tree significant?

 

[alexberka]

Thanks for your comment Staf, I should have phrased my question with “a larger synchronised chip area per watt” ( see my reply to Daniel). I suspect one of the reasons that verification for self-timed logic is not as developed as for synchronous logic, is that the mathematics is significantly more complex. Eg you need a four valued boolean algebra to model the behaviour of logic gates, and this might contribute to a possible combinatorial overhead in the computational cost of verification for self timed circuits, compared with synchronous logic. Is anyone aware of work in this area?

 

[jaweedali]

I'm interested in knowing how this can be achieved reality for existing designs done with synchronous clocks...
Also I'm researching a solution for correct by construction to solve block - block IO timing closure. Without the need to do constraints refinement, etc..
Would appreciate any ideas/leads.

 

[alexberka]

The Tyranny of the Clock

Why worry abut synchronization? Ivan Sutherland puts forward an interesting challenge to clocked systems in http://worrydream.com/refs/Sutherland - Tyranny of the Clock.pdf

There is a caveat in this document: "designing a clock-free system can face the same hard problems of parallelism that give software people nightmares." Many parallel developers find the nightmares so troubling that they are moving away from multi-threading deadlocks, by adopting immune programming methodologies e.g. software transactional memory and the Actor Model. Are such options available to designers of self-timed circuits to address race conditions and the like, without considerable overheads?

 

[LinkedIn]

Al Kwok
Interesting observation! That (clock synchronization where one can approach in a peer-to-peer network or hierarchical structure) is the difference between machine and human. To keep things simple, it is better to have the master clock for a while!