computer power growth

[Herman]

As part of "BIG": Big Data public private forum project, we've studied semiconductor industry forecasts on CPU and memory capabilities. These are the sources:
1. Samuel H.Fuller and Lynette I.Millett (Editors), national research council, “The future of computing performance: game over or next
level?”, 2011. Available at http://orci.research.umich.edu/content/2011/10/2011-Future-of-Computing-Performance-NRC.pdf

2. International technology roadmap for semiconductors, ITRS 20011. Available at: http://www.itrs.net/Links/2011ITRS/2011Chapters/2011ExecSum.pdf

3. Patrick P.Gelsinger, “40years of changing the world”, Intel developer forum, 2008. Available at: http://download.intel.com/pressroom/kits/events/idfspr_2008/2008_0402_IDF-PRC_Gelsinger_EN.pdf

It seems that NRC is quite pessimistic about the future growth rate in CPU/Memory capabilities while Intel (page 15) suggests "the business as usual”
I'll appreciate semiconducting experts’ advice on the difference in those publications and their own opinion on the future of computer power growth (next 5-10 years).

P.S. About "BIG": "BIG" is a project funded by European 7[SUP]th[/SUP] Framework Programme. Building an industrial community around Big Data in Europe is the priority of this project, together with setting up the necessary collaboration and dissemination infrastructure to link technology suppliers, integrators and leading user organizations. As part of this strategy, outcomes of this project will be used as input for Horizon 2020 and will be sustained beyond the project duration. For more information please visit our website: Welcome to BIG - Big Data Public Private Forum! | BIG - Big Data Public Private Forum

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[Daniel Payne]

It may be that Intel is optimistic because they have actually built fabs and designed computer chips, while NRC is a research group that has only designed papers.

On a pragmatic note it has been observed that migrating SoCs to smaller nodes may not be economically attractive, so we may have reached a plateau economically.

I'm looking forward to the next nanotechnology beyond planar CMOS and beyond FinFET to take us into new realms.

 

[Aser]

It means that Intel affords to invest $4,1 bln in ASML to get small project norms, and Nvidia, IBM, AMD, STMicro do not.

 

[Daniel Payne]

Aser,
So the strong IDMs get stronger, and create a wider gap with those IDMs that cannot invest as much..

 

[Aser]

So the strong IDMs get stronger, and create a wider gap with those IDMs that cannot invest as much..

OK. Of course, the players who need now, say, less than a mln. gates will not use the 20 nm norms at all.
The solution is to do without the problems which need that strong IDMs to solve. It is FPGA, or something like this, which provide the ready-to-use transistor formations plus the proper infrastructure. The solution can be the ASSP layer with 20 nm norms plus ASIC layer with 130 nm norms, which form a single 3D chip.

 

[Herman]

But according to ITRS and NRC, No company (including Intel) will be able to increase computer performances with the same rate as before 2003-2004. Would you agree with it?
I mean, we still are able to increase transistors number with the same rate as always but computer performances (in FLOPs) seems to slow down. (or in more accurate way: cost for single computer operation does not decrease with the rate that we were used to before. Where: "cost" is mainly manufacturing costs and energy costs during operation).

 

[Staf_Verhaegen]

It means that Intel affords to invest $4,1 bln in ASML to get small project norms, and Nvidia, IBM, AMD, STMicro do not.

Also TSMC and Samsung have invested which covers a lot of fabless (including Nvidia and part of AMD) .

 

[saurabhr8here]

Its straightforward device physics. With scaling beyond 20nm, moving from planar to fins, the foundries (and Intel) will be able to get about 15~20% improvement in 'device' performance for 2 generations at the most. However, wire RC becomes a killer at these nodes and the overal performance increase per node (with block level and architecture level enhancements) end up being about 10~11%. That is the number that comes up when people run benchmarks between Sandy Bridge and Ivy Bridge processors. With all the FinFET (or Tri-gate) low VDD operation propaganda from Intel, they still run their Ivy Bridge processors in the 0.9~1V range. One of the major hurdles in going to lower supply voltages is IR drops in the metals and reliable power supply in the 0.7V range. Hence Intel is also moving to integrated voltage regulators. Anyway, I won't digress, with my point being, Si Fins can give you only so much benefit. III-V fins are next (7nm?) and then probably nanowires...These will allow us to get more performance/watt if we can solve the wire-scaling problem...

What Intel says in public is a bit of 'PR' involved, so you should take it with a grain of salt. However, they seem to be successfully fabricating devices and pushing the bar on transistors so that says something as well. ITRS is comprised of a bunch of people from the industry (I am a member as well ) who come on a consensus regarding what 'performance' or 'power' we would need in the future and what kind of 'devices' are required to meet that. Their outlook reflects what the industry believes in, but at times it is highly optimistic as well as simply wrong.

 

[pseudosemi]

Great, this last post by saura... touches on just the subject I have been thinking of. That is, the real practical ratio of speed and dynamic power improvement seen on a realistic circuit which takes into effect the (seems to me) increased RC constants between the gates. For example, let's say you synthesize something simple like a 32x32 mutliplier in a few process nodes. what really matters to me is the simple summary of area/performance/dynamic_power/static_power. not to get too fussy, but performance should be at the slow corner, and leakage at the hi temp corner.
At a first pass, that is what matters to me. I am guessing that:

a) from 65 to 40 to 28 the real speed improvement has been modest.
b) the ratio of leakage power to dynamic power ( at max performance speed) has increased.

Building really large chips (FPGA or otherwise) that have alot of transistors sitting around leaking has become more painful.
Can anyone point me to some graphs that show this kind of data???
It seems that things got tougher after 130. by the way, any comparison has to compare LP to LP or G-like to G-like to be useful.