Can China get to 3nm?

[Daniel Nenni]

An optical critical dimension (OCD) model analysis on 3nm complementary FET (CFET) gate stacks

Abstract
In advanced integrated circuit manufacturing technology, the introduction of nanosheet, forksheet, and Complementary Field Effect Transistor (CFET) architectures has created very complicated and dense vertical structures with dimensions as small as several nanometers and with many metallic layers which are not transparent to most optical wavelengths, posing a serious challenge to the metrology. We have provided a scatterometry study on a test pattern design based on the 3 nm logic design rules. Through a simulation study on typical dimensions, we have investigated various linewidths and contact depth with an algorithm based on the Rigorous Coupled Wave Analysis (RCWA).[/TD]

© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Citation Download Citation

Xianhe Liu, Qiang Wu, Qi Wang, and Yanli Li "A study of 3nm CFET middle-of-the-line contact layer OCD measurement sensitivity", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124962Z (27 April 2023); https://doi.org/10.1117/12.2658174

 

[fansink]

An optical critical dimension (OCD) model analysis on 3nm complementary FET (CFET) gate stacks

Abstract
In advanced integrated circuit manufacturing technology, the introduction of nanosheet, forksheet, and Complementary Field Effect Transistor (CFET) architectures has created very complicated and dense vertical structures with dimensions as small as several nanometers and with many metallic layers which are not transparent to most optical wavelengths, posing a serious challenge to the metrology. We have provided a scatterometry study on a test pattern design based on the 3 nm logic design rules. Through a simulation study on typical dimensions, we have investigated various linewidths and contact depth with an algorithm based on the Rigorous Coupled Wave Analysis (RCWA).[/TD]

© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Citation Download Citation

Xianhe Liu, Qiang Wu, Qi Wang, and Yanli Li "A study of 3nm CFET middle-of-the-line contact layer OCD measurement sensitivity", Proc. SPIE 12496, Metrology, Inspection, and Process Control XXXVII, 124962Z (27 April 2023); https://doi.org/10.1117/12.2658174

China will get to 1nm

 

[Jert]

China will get to 1nm

How? Care to elaborate?
E-beam lithography maybe can get to whatever nm needed, but how many chips can be made in a month or in a year?

 

[milesgehm]

The abstract describes work done to measure features that will be present for 3 nm GAA circuit. I don’t see a mention of actually making it.

To answer the question, not in the next 5 years in any volume

 

[Xebec]

Are we talking TSMC or Samsung “3nm”?

 

[fansink]

How? Care to elaborate?
E-beam lithography maybe can get to whatever nm needed, but how many chips can be made in a month or in a year?

Eventually

 

[BruceA]

30 years ago, dang even 15 years ago did we think China would have the cities they have now, the high speed trains, or bet they’d be making their own commercial jet, aircraft carrier or so much more. Don’t discount the competition, it’s clear they scare us so our response is to take away all we can from them to compete versus nurture the unique conditions of the west to compete and out innovate them.

Will be interesting where this tech embargo goes

 

[Fred Chen]

They have an interesting model, 48 nm cell pitch (both directions), 12 nm x 32 nm V0. 868 MTr/mm2.

 

[nghanayem]

30 years ago, dang even 15 years ago did we think China would have the cities they have now, the high speed trains, or bet they’d be making their own commercial jet, aircraft carrier or so much more. Don’t discount the competition, it’s clear they scare us so our response is to take away all we can from them to compete versus nurture the unique conditions of the west to compete and out innovate them.

Will be interesting where this tech embargo goes

Yes, and no lead is forever so to speak. But without hardware capable of ALE, In situ ALD sidewall passivization, cyro, low freq RF, dual RF bias, large diameter process chambers, many ESC temp zones, etc. CFET (something that none of the big three have even demonstrated with a full chip with the best in world equipment available now), and heck even just an okay HNS-FET, seem completely out of reach with late 2000s/early 2010s kit. The aspect ratios and selectivity requirements are simply too much on ancient equipment. That is before we even mention the possibility of bonders or grinders being embargoed, because without BS metalization none of the benefits of CFET would materialize. Or even heck metrology tools to see what the hell you are doing, or deposition/planar tools to make the films that etch is patterning. My opinion is that Chinese equipment vendors improving their offerings are a pre-requisite, and currently they seem to be well over 10 years behind the tier 1 vendors (who themselves aren't just sitting by).

With the jump to SAPQ (which I would assume is an even smaller problem than the above issue since the above is the main enabler of SAPx and SALE^x) there will be a massive step up in number of operations even with more advanced SAPQ techniques/better colors. Every op you add is adding defects so on inferior equipment you will need to have lower DD on your tool just to have comparable EOL DD to TSMC/Intel/Samsung's old news nodes. Then there are also the longer cycle times that slow yield learning and MUCH more restrictive design rules that designers would hate. For an actual 23nm MMP logic process without using pitch multiplication you might have to do something ridiculous like DUV SA-LE^4+ to have slightly more flexible design rules at the cost of many more litho exposures and ALOT more non litho ops to go with. And after that what then? SAPO? SA-LE^6? Maybe some day, but I don't see any way for the 5-6 year gap between TSMC and SMIC to not get wider. The innovation to get N3 and N2 across the line were/are truly extraordinary even with the fanciest toys that the global semiconductor industry can make.

 

[Fred Chen]

They have an interesting model, 48 nm cell pitch (both directions), 12 nm x 32 nm V0. 868 MTr/mm2.

These particular cell dimensions can be achieved with the double-patterning class techniques of SMIC's 7nm. But the difficulty will be patterning vias for the two-tier NMOS and PMOS as well as the backside contacting.

 

[nghanayem]

These particular cell dimensions can be achieved with the double-patterning class techniques of SMIC's 7nm. But the difficulty will be patterning vias for the two-tier NMOS and PMOS as well as the backside contacting.

Yeah the patterning bit was more so if folks wanted to do EUV-less scaled finFET. Even beyond the vias/BS contacts, fin and gate patterning on CFET is verging on DRAM levels of diabolical (because nobody has anything on NAND when it comes to aspect ratios). To say nothing of the precision required for steps like NW release, spacer trim, etc.

image credit DOI:10.3390/mi14091751

image credit: imec

 

[mattyenright]

China will get to 1nm

That will however take a long time to happen, most likely In twenty to thirty years. Before this, the equipment they have will not be able to meet the yield rate, alongside the required production capacity to mass produce it in a significant manner.

 

[KevinK]

They can likely get there using their command economy, but a command economy is a tricky thing to operate. The USSR was able to drive sophisticated space technology and a highly competitive space program using their command economy, yet was unable to deliver consumer goods to its own people, something that eventually caught up with them. China has a similar dilemma, though their command economy seems to incentivize overproduction in key segments, like construction and manufacturing, leading to hyper-competition eventual huge losses in those segments - we're seeing it today in spades construction/housing, and rapidly expanding in chemicals, machinery, automobiles and electronics. These economic misallocations are becoming larger as housing prices decline, domestic consumption dries up and North America and the EU are building barriers to dumping.

Feared in the West, China’s Manufacturers Struggle at Home

Huge overinvestment, weak domestic sales and trade barriers abroad have depressed companies’ profits and pushed many to the brink
Overcapacity drives down prices

The resulting overcapacity means that prices that producers charge at the factory gate have been in free fall for almost two years. That is dragging the overall economy closer to outright deflation, and eating into earnings. Around a quarter of the companies listed in mainland China are now unprofitable, compared with 7% a decade ago, according to a Wall Street Journal analysis of listed companies’ financial statements.

Other countries resist buying China’s excess

Former President Donald Trump has raised the idea of 60% tariffs on all imports from China, while the European Union recently said it was increasing tariffs on Chinese electric vehicles. India, Brazil and Turkey are pushing back against Chinese imports with restrictions and antidumping probes.
Overcapacity is a predictable result of China’s economic system, according to many economists. Beijing routinely directs capital through subsidies, tax breaks and state-controlled banks and investment funds to favored sectors. That gives companies an incentive to pile into those sectors and increase production. China’s auto sector, for instance, is in the midst of a brutal price war as more than 100 companies churn out almost twice as many electric vehicles as domestic drivers buy each year.

Compared with the beginning of 2022, Chinese banks’ real-estate loan books are flat. Loans to industry have swelled more than 60%.

The endgame for money-losing companies
Overcapacity in China eventually leads to default and insolvency, just as in the U.S. The difference is that in China, the state plays a lead role in deciding which companies survive and which fail. In the past, when losses mounted in bloated sectors such as steel and solar, China has withdrawn subsidies, ordered companies to cut capacity, and merged a multitude of minor players into a smaller group of bigger, more competitive firms able to turn a profit.

Feared in the West, China’s Manufacturers Struggle at Home — The Wall Street Journal

Huge overinvestment, weak domestic sales and trade barriers abroad have depressed companies’ profits and pushed many to the brink

apple.news

 

[fansink]

China is not just sitting back and accepting defeat on the EUV embargo, the have likely mandated every major university and the like, to replicate and improve on the art.

Surely, they already have most of the ASML engineering details.

It's not a matter of IF, it's WHEN.

 

[Fred Chen]

There's more of an incentive for China to skip to CFET since it relaxes the lithography requirements, and advances the device at the same time.

 

[KevinK]

China is not just sitting back and accepting defeat on the EUV embargo, the have likely mandated every major university and the like, to replicate and improve on the art.

Surely, they already have most of the ASML engineering details.

It's not a matter of IF, it's WHEN.

But what if that's far from the best allocation of their resources - another Soviet Space Program ?

"Ultimately, by boosting supply more than demand, China is generating growth today but at the cost of growth tomorrow, said Louise Loo, lead economist for China at Oxford Economics. “Whatever you are producing now, you will not produce in the future.”

 

[mattyenright]

China is not just sitting back and accepting defeat on the EUV embargo, the have likely mandated every major university and the like, to replicate and improve on the art.

Surely, they already have most of the ASML engineering details.

It's not a matter of IF, it's WHEN.

I don't doubt they will get there. I never indicated that they will "never" achieve EUV. It's however going to take until 2040 for them to be able to mass produce a machine reminiscent to the ASML EXE 3400c in throughput, stability, coherence, defectivity, and control required for the node of 1nm given the insane level of intrinsic complexities associated with EUV.

It's important to highlight the complexities of each machine given that each ASML EXE:3400c machine has a total of 100,000 parts made by countless companies such as Zeiss Trumpf, Cymer across the Americas, Asia and Europe. This is not the work of a single nation, instead it was a joint effort spanning decades. Even if China has managed to secure most of ASML engineering details, they still need to secure the details and data from the other companies.
`

 

[Fred Chen]

I don't doubt they will get there. I never indicated that they will "never" achieve EUV. It's however going to take until 2040 for them to be able to mass produce a machine reminiscent to the ASML EXE 3400c in throughput, stability, coherence, defectivity, and control required for the node of 1nm given the insane level of intrinsic complexities associated with EUV.

It's important highlight the complexities of each machine given that each ASML EXE:3400c machine has a total of 100,000 parts made by countless companies such as Zeiss Trumpf, Cymer across the Americas, Asia and Europe. This is not the work of a single nation, instead it was a joint effort spanning decades. Even if China has managed to secure most of ASML engineering details, they still need to secure the details and data from the other companies.
`

Most likely they will not take the EUV path: http://www.gdnano.com/?equipmenten/75.html

 

[mattyenright]

Most likely they will not take the EUV path: http://www.gdnano.com/?equipmenten/75.html

I am not fully sure on what you are indicating in respect to nanoimprint lithography. In particular when the information provided in the link does not include key performance metrics such as throughput, defect rate, and template durability.

It's clear that nanoimprint technology has significant potential in assisting with the manufacturing of photonic devices, microfluidics, and flexible electronics, and perhaps NAND, and even DRAM memory. There is however limited evidence that it is capable of meeting the demands for high density logic given its high level of defectivity, overlay, and template durability relative to Extreme ultraviolet lithography (EUV).

Even the most advance version of nanoimprint lithography made by the company of Canon (Molecular Imprints) represented by its machine FPA-1200NZ2C NIL system still does not come close to meeting the requirements for high density logic.

I however fully acknowledge that there could be other methods of alternatives to EUV, and I will applaud China authorities, and companies for investing and perusing new avenues. However, at this current stage, there is no evidence that there are any feasible pathways besides Extreme ultraviolet lithography (EUV) using laser-produced plasma (LPP).

 

[tooLongInEDA]

I don't doubt they will get there. I never indicated that they will "never" achieve EUV. It's however going to take until 2040 for them to be able to mass produce a machine reminiscent to the ASML EXE 3400c in throughput, stability, coherence, defectivity, and control required for the node of 1nm given the insane level of intrinsic complexities associated with EUV.

It's important to highlight the complexities of each machine given that each ASML EXE:3400c machine has a total of 100,000 parts made by countless companies such as Zeiss Trumpf, Cymer across the Americas, Asia and Europe. This is not the work of a single nation, instead it was a joint effort spanning decades. Even if China has managed to secure most of ASML engineering details, they still need to secure the details and data from the other companies.
`

Quite.

Imagine in the EDA world if you found yourself in possession of the entire code base for Synopsys IC Compiler. You'd be able to build the current release. But supporting and maintaining this in the field and building new releases would almost certainly be beyond you. These systems are incredibly complex and a huge part of the knowledge required to operate and maintain them is not in the code/drawings/technical documents.

And who would voluntarily buy such a mission critical and expensive system from a supplier without the confidence that any problems that occur (and they will) can be quickly diagnosed and worked around/fixed ?

Building the ecosystem to create and support such tools is surely the work of decades.