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The presentation discusses the development of an area-efficient SRAM compiler for IHP's SG13G2 open-source process, part of the FlowSpace project funded by the German government. The speaker outlines the SRAM compiler design, emphasizing its simplicity (using a six-transistor cell) and the trade-offs between non-destructive read, write capability, power, performance, and area efficiency. The Arrakeen Python framework is utilized to ensure portability to other technologies like Sky130 and GF180MCU. The project includes radiation-hardening extensions for enhanced resilience. The talk covers the SRAM cell design, block design (including decoders and clock generators), and the challenges of creating a robust, scalable compiler. A test tape-out has been completed, with plans for a refined release by the end of 2025 and further radiation-hardening efforts by April 2026. The SRAM cell is slightly smaller than IHP’s existing design, prioritizing robustness over performance initially, with future optimizations planned.
