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A European Twist on DVCon

MikeBartley

New member
DVCon has been running in Silicon Valley since 1988 but is now going on the road,arriving in Munich, Germany on October 14th and 15th 2014, where it will receive a European makeover. In anticipation, I’ve talked to a number of key people involved to find out what the European slant on DVCon will be.

Accellera Systems Initiative
is a sponsor of DVCon who provide design and verification standards including IP-XACT, SystemC, SystemVerilog, UPF, UCIS and UVM. This gives DVConEurope a strong technical theme and thus a great place for engineers to network.

Stan Krolikoski of Cadence and past Chair of DVCon US likes the small intimate atmosphere of DVCon and explains, “Not everybody can come to Silicon Valley so we want to bring the DVCon to the users in Europe.”

Martin Barnasconi of NXP and General Chair of DVCon Europe explains, “The main theme is learning and sharing through a mix of tutorials, posters, papers and exhibits. DVCon Europe will have a very practical approach where application-specific problems are discussed.”

Oliver Bell of Intel Mobile Communications and DVCon Europe Vice Chair and Tutorial Chair gave a few specific topic examples: heterogeneous system level design, combining AMS [analogue mixed-signal] with hardware-software, and the system-of-systems that are typically part of the development of today’s highly complex electronics-based products.

As DVConEurope Program Vice Chair I will also be speaking at the conference on Requirements Driven Verification and Test(RDVT). This technique is particularly useful for teams developing hardware and software to comply with standards such as ISO26262 for automotive, and DO178C/DO254 for avionics. However, Iwill show how RDVT can improve system development in general.

Hence, DVCon Europe will present a unique opportunity to network and learn from practicing design and verification engineers from across the community. The Accellera sponsored dinner will offer a further opportunity for networking with fellow engineers. Visit the DVCon Europe website to learn more and to register for the event.

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DVCon also happened in India this year and truly it is a great conference. Lot of upcoming technologies have been discussed there. Few of them are

1. Intelligent test bench/ graph based verification - This is not doubt the new verification methodology coming and will replace simulation based verification as the run time requirement just exploding with the increase in design size
2. High Level Synthesis - We were hearing about it for last two decades, but it was not very successful till now. But seems with advancement of tools as well as more adoption of synthesizable high level language (like SystemC) this may become a success now. Besides ASIC, this will have good usage in FPGA design where design turn around time requirement is much more stringent and more complex designs are going into FPGA
3. Design for IoT - The explosion of IoT devices have created new areas of designs like intelligent analog front end, implementation of non volatile logic, dynamic power performance adaptive system etc

Regards,
Barun
 
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