10 nm and 7 nm proceeding at foundries without EUV
- Thread starter Fred Chen
- Start date
EUV is a big transition that seems to always be 24 months out. If GF can get to 7nm without, it makes me wonder if EUV will ever be deployed. After 7 they might be looking for new materials and new processes. It seems that by adding more lithographic based restrictions on layout they can continue to use existing wavelengths for smaller and smaller feature sizes. I am reminded of bubble memory and how it was hailed as the next technology for storage, but magnetic media just kept getting better and better and always stayed ahead of what bubble memory could do.
EUV will still help cut down on the number of layers that require multiple patterning. As you mentioned, it's years too late and missed the opportunity to eliminate multiple patterning for even one node.
The burden of multiple patterning must be reduced but EUV is too defective to be relied upon.
What is so defective about it? The last hurdle seems to be engineering a light source that's powerful enough to achieve reasonable throughput.
Besides, GF isn't a trailblazer in attempting to do 7nm without EUV.
Defects under the multilayer and particles added without pellicle cover since there is no accepted pellicle right now.
Similar arguments could have been made for any litho technology in it's infancy. Or any technology for that matter...
Tom Dillinger
Member
Two years ago, the technical challenges faced by EUV lithography seemed insurmountable:
- low exposure energy
- equipment uptime
- mask blank defects
- metrology for mask blank defects (and compensating mask data placement)
- resist sensitivity
- resist outgassing and mask pellicles
- RET mask data processing requirements (e.g, "shadowing")
to name but a few.
Recent updates would suggest that major strides have been made in each of these areas, although likely too late for 10nm process node development.
With light at the end of the tunnel (pun intended!
), it appears the transition to EUV will be driven by a financial tradeoff, not a technical roadblock.
At 7nm, foundries are faced with the question of the extent to which design rules need to be scaled to provide cost-competitive PPA. A "full scale" from 10nm to 7nm would definitely require that additional multi-patterning be applied to several layers currently using 193i exposure. (One example that comes to mind that has traditionally had conservative rules applied are the "cut" layers.)
In other words, if PPA metrics are sufficient with more restricted design rules and more conservative scaling, the 7nm node may not need EUV (in the 2018 timeframe). If a full scaling is warranted, the cost of EUV for select layers may be advantageous over additional multipatterning in 193i.
-chipguy
- low exposure energy
- equipment uptime
- mask blank defects
- metrology for mask blank defects (and compensating mask data placement)
- resist sensitivity
- resist outgassing and mask pellicles
- RET mask data processing requirements (e.g, "shadowing")
to name but a few.
Recent updates would suggest that major strides have been made in each of these areas, although likely too late for 10nm process node development.
With light at the end of the tunnel (pun intended!
), it appears the transition to EUV will be driven by a financial tradeoff, not a technical roadblock.At 7nm, foundries are faced with the question of the extent to which design rules need to be scaled to provide cost-competitive PPA. A "full scale" from 10nm to 7nm would definitely require that additional multi-patterning be applied to several layers currently using 193i exposure. (One example that comes to mind that has traditionally had conservative rules applied are the "cut" layers.)
In other words, if PPA metrics are sufficient with more restricted design rules and more conservative scaling, the 7nm node may not need EUV (in the 2018 timeframe). If a full scaling is warranted, the cost of EUV for select layers may be advantageous over additional multipatterning in 193i.
-chipguy
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The biggest driver to use EUV at 7nm for some products may not be the wafer production cost, but to cut the exponentially increasing NRE cost resulting from design/verification/mask cost using triple/quad patterning. If only a few very large volume products can afford 7nm this is a big risk to the foundries, all it takes is one customer moving one product to kill the utilisation rates.
Multiple cutting (like LE^4) is definitely not the preferred patterning mode. It is driving the EUV escapism. But I have seen that three colors tops (at most 2 cuts/trims) should be sufficient (even generally) for a 7 nm layer, when the spacer does not pattern the conducting feature (which would have required additional cutting). As for 5 nm node, I can't imagine the gate pitch will go below 40 nm, i.e., no more gate pitch scaling after 7 nm node. Isn't that where the vertical channel GAA is considered for introduction?
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simguru
Member
I'd say the problem with EUV is not whether you can do it, but whether you can do it cost-effectively. There might be some performance advantages to EUV Silicon, but you can probably get better cost per transistor by going 3-D at an older node and tuning the process for lower voltage for lower power.
A lot of the reason for pushing down the nodes is that we want better performance out of an old architecture (Intel particularly), and using better architectures would be a cheaper way to go at this point.
A lot of the reason for pushing down the nodes is that we want better performance out of an old architecture (Intel particularly), and using better architectures would be a cheaper way to go at this point.
user nl
Active member
5nm Test Lights Litho Path Hybrid 193i, EUV seen as best approach
Rik Merritt reports on the hybrid iArF + EUV method to be the most economical as concluded in a IMEC/Cadence project at 5 nm node:
5nm Test Lights Litho Path | EE Times
Rik Merritt reports on the hybrid iArF + EUV method to be the most economical as concluded in a IMEC/Cadence project at 5 nm node:
5nm Test Lights Litho Path | EE Times
Thanks for the link. A recent paper* by GlobalFoundries seems to indicate a throughput of 90 WPH for EUV makes a single exposure as expensive as four 193i exposures. And we are not even at that throughput yet; it's probably equivalent to about six 193i exposures currently. 90wph would require a 250W source at 30 mJ/cm2 dose.
*J. Micro/Nanolith. MEMS MOEMS 14, 023501 (2015)
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