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  1. F

    Build China’s ASML

    NIL is said to target < 10 nm features. The biggest issue is the mask or template, it has tighter defect, placement, roughness, and CD specs than scanner masks, and it also has limited lifetime. The authors did not understand that the SADP is for the template not the wafer. Throughput is also...
  2. F

    Build China’s ASML

    China has been doing EUV research and following ongoing EUV developments, although I don't know if they have been attending the SPIE Advanced Lithography Conferences in person, or if they're banned. But they should know about stochastics. And that TSMC uses multipatterning. (They should...
  3. F

    Build China’s ASML

  4. F

    Build China’s ASML

    Well, taking SMEE as a reference, they're not learning or deploying fast enough.
  5. F

    Intel has manufacturing capacity issues. They may take years to fix.

    The company redirected some of its chips production to meet surging server demand, but analysts say it’s missing out on emerging AI-driven trends. Published March 3, 2026 Nathan Owens Technology companies are clamoring for processors, especially hyperscalers looking to power their data...
  6. F

    Exclusive: ASML plots future of chipmaking tools for AI beyond EUV

    Summary: - ASML plans to expand into advanced packaging for AI chips - Company to use AI to enhance tool performance and production speed - ASML explores larger chip sizes and new scanner systems SAN JOSE, California, March 2 (Reuters) - ASML Holding (ASML.AS), opens new tab has ambitious plans...
  7. F

    Chinese DDR5 RAM: Is This the Solution to Crazy Memory Prices?

    CXMT DDR4 had been at 1x, DDR5 started at 1z. 1c (gamma) is starting to trickle out, but it's still a heavy multipatterning burden (word line pitch < 33 nm).
  8. F

    Intel Board Chair Frank D. Yeary to Retire Following Annual Meeting; Dr. Craig H. Barratt Elected as Chair

    The name really needs a double-take.
  9. F

    Panther Lake design rules revealed, no HD cells

  10. F

    This Innovation Could Make the Perfect Silicon Chip—and End Moore’s Law

    It's slow, like epitaxy, to keep the crystalline order.
  11. F

    This Innovation Could Make the Perfect Silicon Chip—and End Moore’s Law

    I don't know why they couldn't have used one of many available from ASML:
  12. F

    This Innovation Could Make the Perfect Silicon Chip—and End Moore’s Law

    A/MLD is a slow, i.e., expensive, way of depositing photoresist, compared to standard spin-coat.
  13. F

    This Innovation Could Make the Perfect Silicon Chip—and End Moore’s Law

    I can't believe this figure is from TSMC.
  14. F

    Chinese DDR5 RAM: Is This the Solution to Crazy Memory Prices?

    Indeed, the quickly rising prices indicate that their supply is still low.
  15. F

    Chinese DDR5 RAM: Is This the Solution to Crazy Memory Prices?

    CXMT is providing decent DDR5, although the notorious price drop from some weeks ago is now no longer the case. The DDR5 nightmare hasn't eased yet, but today we're checking out an option that might be viable for anyone who needs to get their hands on some memory. As we're all painfully aware...
  16. F

    More Clients Leads to 80% Utilization at Samsung Foundry in 1Q2026

    I had heard about ANAFLASH's 28nm edge AI project back in November: https://www.businesswire.com/news/home/20251103252346/en/ANAFLASH-Advances-Embedded-FLASH-Memory-for-Next-Generation-Smart-Edge-Devices-with-Samsung-Foundry I'd be curious and eager to know if their 8nm eMRAM gets any design...
  17. F

    Samsung enlarges 1c DRAM die size, yields stuck at 60%

    Jukan's source for this post is a ZDNet article: https://zdnet.co.kr/view/?no=20260225154303#_enliple Samsung Electronics' breakthrough was the "enlargement of the chip size" of its 1c DRAM. Around the end of 2024, Samsung Electronics decided to revise some of its 1c DRAM design. The key point...
  18. F

    Samsung enlarges 1c DRAM die size, yields stuck at 60%

    Samsung Electronics made the decisive move to enlarge the die size of its core die, the 1c (6th-generation 10nm-class) DRAM. A larger die size can simultaneously improve the stability of both DRAM and HBM4. However, this decision works unfavorably from a profitability standpoint, as it reduces...
  19. F

    Panther Lake design rules revealed, no HD cells

    Next best thing is to check the teardowns.
  20. F

    Exclusive-ASML unveils EUV light source advance that could yield 50% more chips by 2030

    Exactly. Higher heating and stronger EUV-induced plasma effects, resist degrading/thinning faster.
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