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Samsung Electronics made the decisive move to enlarge the die size of its core die, the 1c (6th-generation 10nm-class) DRAM. A larger die size can simultaneously improve the stability of both DRAM and HBM4.
However, this decision works unfavorably from a profitability standpoint, as it reduces the number of chips producible per wafer. Additionally, with 1c DRAM yields still hovering around 60%, opinions have emerged that Samsung Electronics must accelerate process maturation as quickly as possible.
Samsung's 1C DRAM (6th-gen 10nm-class) is currently expected to use 6 to 7 EUV (Extreme Ultraviolet) layers. Although Samsung originally planned to use 8–9 layers, they have reduced the count to improve production yield and process stability.
SemiWiki +2 Key Details on Samsung's 1C DRAM:
EUV Layer Count: Reduced from a planned 8-9 down to 6-7 layers.
Material Shift: Samsung is considering using Metal Oxide Resist (MOR) for the finest circuitry layers in 1C DRAM to enhance patterning, rather than relying solely on traditional photoresists.
Application: The 1C DRAM process is expected to be utilized in high-performance, high-density products, including DDR5 and HBM4.
Production Timeline: Mass production of 1C DRAM is planned to start in the second half of 2025.
SemiWiki +3
Note: While some reports initially suggested higher EUV adoption, 6-7 layers is the currently reported target for balancing performance and yield.
SemiWiki
As of early 2025, the strategies regarding Extreme Ultraviolet (EUV) lithography for DRAM production have diverged significantly among the three major manufacturers. SK Hynix has emerged as a leader in extensive EUV adoption Samsung is aggressively using it to catch up in high-bandwidth memory (HBM) yields, while Micron has adopted a more conservative"EUV-light" approach, relying more on traditional ArFi (Argon Fluoride immersion) lithography for its 1beta and 1gamma nodes
EUV Usage Comparison (2025–2026)
SK Hynix (Aggressive Adopter): Leads in EUV usage for advanced nodes. For 1c DRAM (6th-gen 10nm-class), they are moving to use five or more EUV layers, up from four layers in 1b. They are also preparing for High-NA EUV adoption to maintain a performance edge.
Samsung (High-Volume Adopter): First to introduce EUV in 2020. Samsung plans to apply over five EUV layers to its 1c DRAM, focusing on increasing layer counts for 1c and future HBM4 to overcome previous yield issues.
Micron (Conservative/Selective Adopter): Has pursued a strategy of minimizing EUV usage, relying heavily on DUV (Deep Ultraviolet) and ArFi to reduce costs, only using EUV for critical, essential layers (often just one layer on earlier nodes). However, Micron is beginning to use EUV for 1gamma
Samsung Electronics' breakthrough was the "enlargement of the chip size" of its 1c DRAM. Around the end of 2024, Samsung Electronics decided to revise some of its 1c DRAM design. The key point was to maintain the line width of core circuits while relaxing some of the line width standards for peripheral circuits, thereby reducing the difficulty of mass production.
According to internal and external reports from Samsung Electronics, the expansion of 1c DRAM size has had two major effects. First, it has improved 1c DRAM yields. With peripheral circuit implementation becoming easier than before, Samsung Electronics' 1c DRAM yields are improving at a relatively steady rate. Industry estimates suggest that Samsung Electronics' 1c DRAM yield for HBM4 is in the 50-60% range as of this month.
Furthermore, the expanded chip size is believed to have secured stability in the TSV (Through Silicon Via) process, which is essential for HBM manufacturing. HBM4 requires more TSV holes in DRAM due to the increased number of I/Os compared to its predecessor. Samsung Electronics' 1c DRAM has a larger available area, allowing for relatively more leeway in TSV placement. This reduces TSV density, making it easier to manage heat and ensure reliability.
