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  1. F

    Intel CFO confirms that 14A will be more expensive than 18A due to High-NA EUV tool

    The practical resolution is determined by stochastics not NA.
  2. F

    SK Hynix adopts next-generation HNA-EUV ASML production equipment for DRAM

    It looks like they made an array, although not mentioning the array size or dimensions.
  3. F

    SK Hynix adopts next-generation HNA-EUV ASML production equipment for DRAM

    SK Hynix did 5 layers for VLSI 2024: https://www.businesskorea.co.kr/news/articleView.html?idxno=219741
  4. F

    Samsung does not use EUV pellicles; FST in talks with Samsung to supply EUV pellicle

    I found an interesting excerpt from here: https://globaltechresearch.substack.com/p/carbon-nanotube-cnt-the-next-big Not only do memory manufacturers not use EUV pellicles, but even TSMC tries not to use EUV pellicles too much in their advanced node process, due to their high cost (over $10,000...
  5. F

    SK Hynix adopts next-generation HNA-EUV ASML production equipment for DRAM

    Since there will be many layers (like in 3D NAND), the capacitors can be spaced further apart, not requiring the highest resolution anymore. The issue with 4-6 F^2 is that distances between different features that can couple capacitively are getting too close. For 4F^2, there is the additional...
  6. F

    Samsung does not use EUV pellicles; FST in talks with Samsung to supply EUV pellicle

    Without pellicles, periodic inspections are needed to infer particles on the mask before too many dies are lost. The inspection cost could force some yield risk to be accepted. https://www.researchgate.net/publication/331763063_Advanced_particle_contamination_control_in_EUV_scanners
  7. F

    SK Hynix adopts next-generation HNA-EUV ASML production equipment for DRAM

    The thing about 4F2 is it has a short runway. The channel material also seems not settled yet (also applies to 3D DRAM).
  8. F

    Samsung does not use EUV pellicles; FST in talks with Samsung to supply EUV pellicle

    JY Han 승인 2025.09.03 07:35 Supply could start within year FST was holding talks with Samsung on the price of extreme ultraviolet (EUV) pellicles that it will supply to the South Korean chipmaker, TheElec has learned. The back and forth on the price of the commodity used in advanced chips...
  9. F

    SK Hynix adopts next-generation HNA-EUV ASML production equipment for DRAM

    SK Hynix should be worried about what's really limiting DRAM scaling. As I've said here: https://semiwiki.com/forum/threads/sk-hynix-presents-future-dram-technology-roadmap-at-ieee-vlsi-2025.23427/#post-90937 6F² scaling is now coming up against the issue of shrinking gap between bit line and...
  10. F

    YMTC to collaborate with CXMT on HBM

    The Chinese semiconductor industry's commitment to and pursuit of HBM (High Bandwidth Memory) development is strong. Yangtze Memory Technology (YMTC), a major local NAND manufacturer, is also reportedly conducting research and development on DRAM and seeking collaborations with major local DRAM...
  11. F

    Stochastics: Yield-Killing Gap No One Wants to Talk About

    Recent outgassing studies have pinned down resist degrading significantly (losing >10% of key component) with EUV doses above 50 mJ/cm2: https://frederickchen.substack.com/p/euv-resist-degradation-with-outgassing
  12. F

    Rapidus Announces Strategic Collaboration with Keysight To Improve Yield and Achieve High-Precision PDK For 2nm GAA Semiconductors

    TOKYO, Aug. 26, 2025 — Rapidus Corporation, a leading-edge Japanese foundry that manufactures advanced logic semiconductors, today announced a strategic collaboration with Keysight Technologies Japan K.K., the Japanese subsidiary of Keysight Technologies, Inc., and has signed a Memorandum of...
  13. F

    SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025

    The 3D NAND could use vertical polysilicon channels, while the 3D DRAM needs horizontal channels, preferably not polysilicon. Reliability is of utmost importance, so SLC is a must.
  14. F

    The Fall of Intel

    A couple of interesting, very likely debatable, points from Professor Bill Lazonick in this video: 1. It looks like he feels Intel did too much stock buybacks, much more than R&D investment, due to their importance to compensation. 2. He suggests PG got the boot due to close ties with Biden, in...
  15. F

    SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025

    6F² scaling is now coming up against the issue of shrinking gap between bit line and storage node contact. On the other hand, 4F² has the issue of word lines too close for cell sizes <0.0009 um². So 3D DRAM probably should be expedited...
  16. F

    How are the benefits of BSPD affected by 3D stacking?

    https://tspasemiconductor.substack.com/p/the-thermal-frontier-of-bspdn-iitc At the 2025 IEEE ECTC, TSMC unveiled several advanced thermal management solutions aimed at addressing the challenges posed by high power density chips. These include innovations in thermal interface materials (TIMs)...
  17. F

    SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025

    Seoul, June 10, 2025 SK hynix Inc. (or “the company”, www.skhynix.com) announced today that it presented a new DRAM technology roadmap for the next 30 years and the direction for a sustainable innovation at the IEEE VLSI symposium 20251 held in Kyoto, Japan. Cha Seon Yong, Chief Technology...
  18. F

    Stochastics: Yield-Killing Gap No One Wants to Talk About

    Despite continuous improvements in the performance of EUV photoresists, EUV masks, and post-lithography processes, stochastic defects, or stochastic failures – space bridges and line breaks - are still a major factor of yield loss in EUV production. The detection of stochastic defects is...
  19. F

    Forget the White House Sideshow. Intel Must Decide What It Wants to Be.

    Yeah, there's a big gap from R&D to manufacturing. Volume needs and breeds statistics. Let's not also forget N5 D0>1/cm2 (on average!) at risk production: https://web.archive.org/web/20200525115643/https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020.
  20. F

    Government’s Intel intervention is ‘essential’ for national security, tech analyst says

    Published Fri, Aug 15 202510:21 AM EDT Updated Fri, Aug 15 20254:07 PM EDT Annie Palmer@in/annierpalmer/@annierpalmer Key Points - Government intervention in Intel is “essential” to protect U.S. national security, analyst Gil Luria said. - Bloomberg reported that the Trump administration is...
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