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There was an interesting statement possibly alluding to relative die size:
According to industry sources on the 16th, the test production yield of logic dies produced by Samsung Electronics' foundry 4nm (nanometer, 1 billionth of a meter) process has exceeded 40%. Considering that the initial...
Probably in the race at leading edge (or actually any popular advanced node) to be "first" (or simply participate), yield requirements were loosened. Not even months' delay from new design tapeout.
While the foundry (semiconductor contract manufacturing) process is applied to the 'logic die', which serves as the brain of the 6th generation high-bandwidth memory (HBM4), for the first time, it is known that the test yield of the logic die produced by Samsung Electronics' foundry division is...
I am a bit surprised that their SAC would get in the way of their gate cut. Granted that it's getting very tight there. The directly focused spot size of EUV is 25 nm, so it's too large for the contact sizes I was expecting.
By Paul Alcorn
At its Vision 2025 conference, Intel announced today that it has entered risk production of its 18A process node, a crucial production milestone signifying that the node is now in the early stages of low-volume test manufacturing runs.
Intel's Kevin O'Buckley, the Senior Vice...
I had the impression the main changes were EUV reduction and pitch relaxation.
The nanosheet pitch design rules should be roughly half the smallest cell height ~65 nm, it should be comparable to N16 MMP.
Not saying they shouldn't have done it, just the timing is politically not optimum. They hopefully are not rushed this time as with the Meteor Lake. Did Ireland ever give the energy subsidy?
For 1C, the bit line pitch is ~36 nm, which is hitting that limit. The word line pitches and active area pitches are even smaller.
MMP is above 40 nm, making use of difficult double patterning.
Guided by TSMC https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12751/127510N/EUV-APSM-mask-prospects-and-challenges/10.1117/12.2688111.short, 18 nm CD is too small in darkfield layers, and ASML...
For DRAM, there is no rapid increase in mask count as seen with logic. Instead there are changes such as from direct print to SADP to SAQP, but these are long established processes (for the DRAM/Flash makers). There was a mention of combining some array patterns with peripheral patterns in one...
Seyeon Lee 2025.03.19 07:00:37
The number of EUV layers will be reduced by 30% compared to the plan 2~3 years ago
Samsung Electronics, which is making an all-out effort to secure yields, has decided to reduce the number of layers of extreme ultraviolet (EUV) lithography equipment from the...
