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That is my memory as well. I mostly included it because I think it is funny. I don't think anything in industry has ever looked that obviously impractical. When Samsung was doing that, TSMC's DUV SALELE flow (which I think debuted on N7, but maybe it was on 10FF) would have been unknown to...
This news is over a year old. Intel has mentioned that which one they use will depend on which one is better almost a half dozen times at this point. Parallel developments and derisking high risk items were two of the things Ann K said she changed about how Intel does development during...
That same statement could be said of regular EUV too. DUV uses far thicker resits and is far less defective than EUV per pass, but you hardly see logic folks using multipaterning DUV for much these days. Non spacer based quad patterning was dead before low-NA EUV even hit its stride. The one...
I mean yeah. But you say that as if there will never be any situations from now till the end of time where high-NA will ever be more cost effective than low NA. Intel has said time and time again they will ONLY pull the trigger if it is the best PPAC path and that based on the data they see...
You say that as if it isn't the right PPAC choice for Intel. Also Samsung hasn't made a public commitment to anything. Not every process is the same and what works well for one process won't necessarily work for another. As an example Intel by fully embracing BSPD can use much wider metals for...
I mean they did write down like $10B+ of equipment and take down a lot of intel 7 capacity because they thought they wouldn't need it. So that can't exactly help matters. For the U series, there are traditionally two types of laptop they go into. Cheap, and premium low power. MTL/ARL-U were...
That's easy. So they continue to be Intel foundry customers in the future, and so you can win more and bigger designs going fowarwd.
I wouldn't really call Amazon or Microsoft AI chips as key customers, nor would I call a DoD chip key. Those are all small fries. While not an 18A design win, I...
Intel Foundry's website says they have 9 locked in 18A foundry customers. Only Microsoft and Amazon are publicly named. Maybe BCOM is already committed? Because they slammed down Reuters real fast when they ran that BCOM being upset that 18A wasn't HVM ready like 4 months before Intel even said...
Well you see you are wrong. Morris Chang and the echo chamber of the internet said American worker are stupid dumb and lazy, and what Taiwan has cannot be replicated. Your data is invalid :cool:
Why? If anything yield should have started about where Taiwan is right now since TSMC said for their...
Your assumption is too optimistic. And the reason for that is shipping time and advanced packaging. With the one quarter cycle times of N2 and slightly less than a quarter cycle times on N3 Apple needed wafers to start in December just to have volume of final assembled iPhone pro only by...
It isn't a joke, or at least not one he consciously made. He would always call the Camas Washington fab the Oregon fab. And it really drives home just how much of a backwater that operation was and how little Morris thought of those employees that he didn't even know where the fab that was built...
Oh that's what you were getting at. Yeah no comment from me since that isn't a topic I have any insight into and I don't want to just make stuff up. That isn't how I roll.
If you'd look you'd also see the new Japan fab is also losing money. This is normal for a new fab that is starting up. Fab20 in Taiwan is bleeding money like nobody's business until a larger percentage of the tools get set and the money starts getting rolled in by the dump truck for those N2/A16...
Maybe I don't understand what you are saying but the Vdroop isn't super useful for low voltage (like Xeons or most leading edge foundry customers) situations. The bigger benefit is for reducing high V heat/power (desktop and laptop CPUs); at least that is my understanding. Low threshold voltage...
Yes literally. There is no faith required. CC Wei himself has said the very first production wafer will not start until a quarter after iPhone 17 launch and the very first production wafer will not leave a TSMC fab until 2026. It is by definition impossible for there to be N2 anything in 2025...
Funny all the edditoaliztion of what wasn't said. They edditors are talking as if this wasn't already the case. Oh surely Intel foundry sucking is why core IP is 99% process agnostic. But then ignore Intel saying last year that Lion cove and crestmont are 99% process agnostic. The process...
You've hit the nail on the head. I don't think anyone can argue that Pat underestimated the task in front of him. The pandemic boom lulled Intel into a false sense of security that all they needed to do was fix TD, build new fabs to support EUV nodes, and gradually build out a solid foundry...
I fail to see how any of this helps CCG, DCAI, or NEX become world class. In fact you just proved my point by putting Tan on a pedestal despite not having done anything yet. Other than Sandra none of the people you mentioned even have any indication they have been sacked.
Initial work is far...
I mean there weren't exactly any bad signs in my book. This is a better sign for AMD then TSMC in my book since TSMC was always getting the buisness. IMO the question was always when AMD N2 products would launch not if.
Absolutely not. Unless TSMC has invented time travel and took the wafers...
Not buying it. Smart money is on iPhone 18 being the first product. With cycle time being what it is N2 HVM start is perfectly lined up for IPhone 18 ramp. N3 HVM started in December 22 and N3 chips showed up for the 15 pro in September 23. And CC has reiterated time and time again that N2 is...
