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Intel CEO Lip-Bu Tan appears to be adopting a go-it-alone strategy as he embarks on rebooting the chip giant.
By Therese Poletti
Last Updated: April 17, 2025 at 7:01 p.m. ET
Intel Corp.’s stock recently rode a wave of enthusiasm around potential deals or partnerships that could make its...
TechInsights will probably follow up on this, but they had felt that 6 nm (N+3) may actually just be a closer approach to TSMC N7 than N+2.
https://library.techinsights.com/hg-asset/082ca072-8e6f-4d09-a0eb-2b1c65353e9f
It looks like Intel's HP and HD cells are differentiated by track pitch (36 nm vs. 32 nm), with fixed track number (5), whereas TSMC has fixed track pitch (26 nm) and differentiates by track number (6 vs. 5). Two pitches is more complicated lithographically (different pitches focus differently).
The higher power of the FEL means mirror damage is a new concern, e.g., https://www.sciencedirect.com/science/article/abs/pii/S0925346725003222#
Probably a hydrogen plasma is still needed to keep the mirrors clean and cooled.
Pat Gelsinger, former CEO of Intel, recently posted on LinkedIn that he joined xLight as executive chairman, and the xLight official website also announced the news in March.
xLight is the company that develops a linear electron accelerator for extreme ultraviolet (EUV) lithography machines...
There was an interesting statement possibly alluding to relative die size:
According to industry sources on the 16th, the test production yield of logic dies produced by Samsung Electronics' foundry 4nm (nanometer, 1 billionth of a meter) process has exceeded 40%. Considering that the initial...
Probably in the race at leading edge (or actually any popular advanced node) to be "first" (or simply participate), yield requirements were loosened. Not even months' delay from new design tapeout.
While the foundry (semiconductor contract manufacturing) process is applied to the 'logic die', which serves as the brain of the 6th generation high-bandwidth memory (HBM4), for the first time, it is known that the test yield of the logic die produced by Samsung Electronics' foundry division is...
I am a bit surprised that their SAC would get in the way of their gate cut. Granted that it's getting very tight there. The directly focused spot size of EUV is 25 nm, so it's too large for the contact sizes I was expecting.
By Paul Alcorn
At its Vision 2025 conference, Intel announced today that it has entered risk production of its 18A process node, a crucial production milestone signifying that the node is now in the early stages of low-volume test manufacturing runs.
Intel's Kevin O'Buckley, the Senior Vice...
I had the impression the main changes were EUV reduction and pitch relaxation.
The nanosheet pitch design rules should be roughly half the smallest cell height ~65 nm, it should be comparable to N16 MMP.
