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Search results

  1. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    I thought they presented SALELE with one block mask. Actually, it is usually presented with two block masks, one for each of the two metal line sub-patterns. I suppose it depends what they count as a "step". 24-32 nm pitch on 0.33 NA is just like 24-30 nm pitch on 0.55 NA. I don't know if the...
  2. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    With a direct print at this pitch they won't be able to shrink this layer lengthwise, also due to the tip-to-tip distance.
  3. F

    TSMC vs Intel track pitch scaling trend

    6-track cell height scaling trend shows an interesting comparison between TSMC and Intel. PowerVia gave opportunity to relax the track pitch at Intel 18A. In the meantime, the track pitch scaling slowed down dramatically for TSMC. Perhaps it's coincidental with nanosheet introduction?
  4. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    3 exposures with many more steps is an odd process integration. This is for 18A node?
  5. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    In my recollection, it was merely from the drawing of the HD and HP cells, both appeared to be 5 tracks, and the cell heights are 160 and 180 respectively. Both size and spacing matter for the pitch dependent best focus.
  6. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    This is P32 HD P36 HP IIRC, the two pitches don't focus the same in direct print.
  7. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    Just viewing it as a kind of disclaimer, looked like fine print to me.
  8. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    Our knowledge of EUV is always growing. Earlier on much less was known, so we can expect a fast buildup of an EUV fleet without knowing any better, and using them maximally, at least to get as much key data as possible. But now I expect people to be more careful. Especially with the newly...
  9. F

    Intel Foundry Gathers Customers and Partners, Outlines Priorities (Intel Connect Live)

    "Results may vary." :ROFLMAO: They talk about enabling direct print, but at the same time the 40-step multipatterning (3 masks) was broadcast widely as well.
  10. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    LELELELE was mainly shown by Samsung at 8nm if I recall correctly. The difficult with more than two LEs is the CD/pitch ratio is too low, so NILS (normalized image log-slope) is bad. This I doubt, since the fin pitch is so small. EUV DP still too expensive and more issues than DUV SAPQ. DUV...
  11. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    So far High-NA still gives bad images even at 28 nm pitch. To be fair low-NA should be the same. High-NA has less depth of focus so needs thinner resist, which tends to be more defective.
  12. F

    TSMC Is Reportedly Skipping High-NA EUV For The A14 (1.4nm) Process; Prioritizing Cost-Efficiency Over Performance

    The author of this article doesn't know what he is talking about it, as he writes that Intel 18A will use High-NA. Interestingly, TSMC's decision to leave high-NA EUV behind does put the company behind the likes of Intel Foundry in adopting the latest tools, since Team Blue is said to utilize...
  13. F

    Huawei, the leader in Chinese semiconductor development… ‘Life or death’ for SMIC 5nm mass production next year

    It's interesting or useful as a replacement for CO2 lasers regardless of application. But this technology is already well-established, such as Nd:YAG laser.
  14. F

    ASML’s Breakthrough 3-Pulse EUV Light Source

    It always struck me as a little disingenuous to report throughput at a dose of 20 or 30 mJ/cm2, when it should be reported at 50-60 mJ/cm2. With powers of 500W already available, it should be easier to present?
  15. F

    Huawei, the leader in Chinese semiconductor development… ‘Life or death’ for SMIC 5nm mass production next year

    There were reports Ascend 920 is made on a "6nm" by SMIC. If TechInsights can analyze it, we might see their actual current progress or where they're stuck. "6nm" might still be practically the same design rules as TSMC N7. N5 EUV still needed double patterning but the corresponding DUV...
  16. F

    Huawei, the leader in Chinese semiconductor development… ‘Life or death’ for SMIC 5nm mass production next year

    If the SiCarrier process is used, that would be interesting. The low yield predictions are associated with the (LE)n style of multipatterning. SAQP-based is much simpler but is more fitting for elongated, limited pitch layouts.
  17. F

    Intel Reportedly Places 2nm Orders For Nova Lake At TSMC; Foundry Division Likely To Be Left Out For Now

    UBS hinted NVIDIA and Broadcom may have had some feedback on 18A, preferring 18AP instead: https://www.marketwatch.com/story/it-looks-like-intel-may-have-to-go-it-alone-can-ceo-lip-bu-tan-fix-the-company-solo-b22b54d2 But that shouldn't affect the plans for Intel Product. Tim Arcuri, a UBS...
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