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Search results

  1. F

    CXMT 17nm DDR5 yield rate has reached 80%

    "The US has been trying to restrict China from developing high-end chip production capabilities, while seeking to avoid disrupting its production of commodity chips." https://www.silicon.co.uk/e-regulation/us-china-japan-chip-memory-591866 Reportedly, CXMT was recently excluded from the...
  2. F

    CXMT 17nm DDR5 yield rate has reached 80%

    This indicates significant progress in multipatterning yield.
  3. F

    CXMT 17nm DDR5 yield rate has reached 80%

    China Changxin Storage's DDR5 yield rate has reached 80%, and it is also striving to produce HBM2 in small quantities by 2025 (Auto-translation) Written by Atkinson | Release date: 2025-01-03 9:30 | Foreign media reported that China's third-party memory module manufacturers began to sell DDR5...
  4. F

    Trump's Undersecretary of Defense for Policy repeatedly said TSMC fabs should be destroyed if China invades Taiwan

    That would be impossible to happen: https://www.tomshardware.com/tech-industry/tsmc-cannot-produce-2nm-chips-overseas-until-domestic-output-becomes-more-advanced-confirms-taiwanese-govt-official Taiwanese regulations require domestic chipmakers to manufacture only chips using...
  5. F

    KSMC to challenge TSMC with Samsung expertise?

    Seems China would be a bigger threat than TSMC for legacy and mid-tech nodes.
  6. F

    KSMC to challenge TSMC with Samsung expertise?

    Published 26 mins ago on December 26, 2024 By James Lee Taylor South Korea considering forming KSMC to challenge TSMC with Samsung expertise. The name of this organization, Korea Semiconductor Manufacturing Company, is purely inspired by the Taiwanese Semiconductor Manufacturing Company (TSMC)...
  7. F

    Trump's Undersecretary of Defense for Policy repeatedly said TSMC fabs should be destroyed if China invades Taiwan

    So they don't know of or believe in the equipment disablement in case of an invasion?
  8. F

    CEO of ASML speaking on Chinese Semicon

    Two months ago, he did acknowledge they could have the means to do even 3nm: https://wccftech.com/asml-ceo-believes-that-china-might-be-able-to-produce-chips-on-the-5nm-and-3nm-nodes-on-a-limited-scale/ Of course, whether they are actually there is a different story, though Xiaomi is reported...
  9. F

    Russia has written a “road map” for creating a sovereign lithograph cheaper and simpler than ASML

    11.2 nm has more stochastics and energetic electrons. They sound like they are starting from the 20th century knowledge.
  10. F

    Could Pat Gelsinger be reinstated as Intel's CEO?

    Seems the board would have to go for that to happen.
  11. F

    Intel Foundry Fails To Impress Once Again, 18A Process “Yield Rates’ Are Reported To Be Only 10% Making Mass-Production Impossible FROM wccftech

    Assuming Broadcom was a customer, it would have received PDK 1.0: https://hwbusters.com/news/intels-18a-faces-challenges-with-broadcom-while-20a-plans-for-arrow-lake-are-canceled-for-foundry-customers/ So PM's comment suggests they got the bad results with an older PDK.
  12. F

    Intel Corporation to Participate in Upcoming Investor Conferences

    I thought this meant that Intel products would be the main driver of foundry revenue in the short term.
  13. F

    Intel Corporation to Participate in Upcoming Investor Conferences

    Two statements from Naga give reason to be wary: 1. "And 18A, our biggest customer for the next two, three years is still Intel products," 2. "Now it is about going through the remaining yield challenges, defect density challenges, continuing to improve it, improving process margin and getting...
  14. F

    Intel 18A "too good" but design lags

    I just read Naga Chandrasekaran saying that 18A still had defect density challenges and milestones to achieve. https://seekingalpha.com/article/4742201-intel-corporation-intc-ubs-global-technology-and-ai-conference-transcript
  15. F

    TSMC's N2 process has a major advantage over Intel's 18A: SRAM density

    He's using a formula 0.667/density (Mb/mm2) to give SRAM cell size, but it's definitely not a fixed formula.
  16. F

    TSMC starts equipment installation for 2nm fab

    No high-NA because there is stitching. Moreover, the EUV community knows (but doesn't like to announce widely) that high-NA requires a different EUV mask substrate than the 0.33NA.
  17. F

    Intel 18A "too good" but design lags

    Intel 18A has two sets of interconnects (backside and frontside) which have to be separately aligned and patterned. TSMC A16 would be the same. https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
  18. F

    Inside Intel’s Lunar Lake: A Promise That Became a Problem

    TSMC doesn't supply the DRAM that is bundled into the packaging. It just meant relying on TSMC is unfavorable for Intel's cost structure.
  19. F

    Inside Intel’s Lunar Lake: A Promise That Became a Problem

    郭明錤 (Ming-Chi Kuo) Nov 5, 2024 Intel has recently announced that after Lunar Lake (LNL), it will discontinue integrating DRAM into CPU packaging. While this news has caught public attention recently, people working in the PC industry have known for at least six months — according to Intel’s...
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