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What are the historical and probable future node yields from Intel, Samsung, and TSMC?

fansink

Active member
I understand that answers to this question are not easily obtained, but your expert opinion is valuable.

Now that lower than risk yields (-20%) are passing for “generally acceptable” HVM yields (+70%), for political, marketing, and besting the competition reasons, at least, I’m sure many readers would love to have information on the historical and probable future node yields from Intel, Samsung, and TSMC.

Further, IMO, investors and foundry clients should have the right to know the true yields, as it can comparatively help to determine competence and value.

Especially since we now know that Samsung has admitted to falsifying yields on their 4nm and 3nm nodes and possible larger nodes as well. When investors and foundry clients learned the truth, many severed ties.

Maybe voluntary independent auditing should become a thing.

I have a strong feeling that the pressure Intel is under, least of which may be their very existence, may have been miraculously resolved (5 nodes in 4 years), by deciding to release nodes with less that “generally acceptable” yields.

Intel has apparently released 10nm chips with ~20% yields and was discussed here at SemiWiki.

https://semiwiki.com/forum/index.ph...estion-about-the-10nm-yield.13594/#post-45170

https://www.notebookcheck.net/Tough...production-outsourcing-and-more.509532.0.html
 

hist78

Well-known member
I understand that answers to this question are not easily obtained, but your expert opinion is valuable.

Now that lower than risk yields (-20%) are passing for “generally acceptable” HVM yields (+70%), for political, marketing, and besting the competition reasons, at least, I’m sure many readers would love to have information on the historical and probable future node yields from Intel, Samsung, and TSMC.

Further, IMO, investors and foundry clients should have the right to know the true yields, as it can comparatively help to determine competence and value.

Especially since we now know that Samsung has admitted to falsifying yields on their 4nm and 3nm nodes and possible larger nodes as well. When investors and foundry clients learned the truth, many severed ties.

Maybe voluntary independent auditing should become a thing.

I have a strong feeling that the pressure Intel is under, least of which may be their very existence, may have been miraculously resolved (5 nodes in 4 years), by deciding to release nodes with less that “generally acceptable” yields.

Intel has apparently released 10nm chips with ~20% yields and was discussed here at SemiWiki.

https://semiwiki.com/forum/index.ph...estion-about-the-10nm-yield.13594/#post-45170

https://www.notebookcheck.net/Tough...production-outsourcing-and-more.509532.0.html
I understand that answers to this question are not easily obtained, but your expert opinion is valuable.

Now that lower than risk yields (-20%) are passing for “generally acceptable” HVM yields (+70%), for political, marketing, and besting the competition reasons, at least, I’m sure many readers would love to have information on the historical and probable future node yields from Intel, Samsung, and TSMC.

Further, IMO, investors and foundry clients should have the right to know the true yields, as it can comparatively help to determine competence and value.

Especially since we now know that Samsung has admitted to falsifying yields on their 4nm and 3nm nodes and possible larger nodes as well. When investors and foundry clients learned the truth, many severed ties.

Maybe voluntary independent auditing should become a thing.

I have a strong feeling that the pressure Intel is under, least of which may be their very existence, may have been miraculously resolved (5 nodes in 4 years), by deciding to release nodes with less that “generally acceptable” yields.

Intel has apparently released 10nm chips with ~20% yields and was discussed here at SemiWiki.

https://semiwiki.com/forum/index.ph...estion-about-the-10nm-yield.13594/#post-45170

https://www.notebookcheck.net/Tough...production-outsourcing-and-more.509532.0.html
IMHO, Qualcomm and Nvidia knew the yield issues at Samsung very well. They might try to give Samsung enough room and extra time to improve it until they can't wait anymore. It's in their best interest to support Samsung in order to have a TSMC alternative.
 
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fansink

Active member
Thanks Fred, that sounds awesome. What is the accuracy of your model, and are you able to share any of your results?
 

prime007

Active member
Maybe that's why rumor has it that Intel and Apple will be TSMC's two biggest costumers for N2?

 

Fred Chen

Moderator
Thanks Fred, that sounds awesome. What is the accuracy of your model, and are you able to share any of your results?
It won't really help you directly estimate yield, but gives an idea of relatively how the companies are doing.

Intel: https://www.theverge.com/2022/1/26/22903138/intel-q4-2021-january-2022-earnings-best-year
30 million Tiger Lakes sold, margin over 50%

TSMC:
Using iPhone13 shipments as an indicator, obviously doing well: https://www.imore.com/iphone-shipments-hit-record-855-million-fourth-quarter-2021
Margins: net ~38% (not just 5nm), gross margin also over 50%
https://investor.tsmc.com/chinese/e...12fc3ba28169ec091a86/4Q21ManagementReport.pdf

Samsung:
Galaxy S22 as indicator of Samsung 4nm, there have been delays: https://www.tomsguide.com/news/samsung-galaxy-s22-delays-heres-the-ship-date-for-each-model-now
Margins: 34% (all semiconductor) https://news.samsung.com/global/samsung-electronics-announces-fourth-quarter-and-fy-2021-results
 
Last edited:

fansink

Active member
It won't really help you directly estimate yield, but gives an idea of relatively how the companies are doing.

Intel: https://www.theverge.com/2022/1/26/22903138/intel-q4-2021-january-2022-earnings-best-year
30 million Tiger Lakes sold, margin over 50%

TSMC:
Using iPhone13 shipments as an indicator, obviously doing well: https://www.imore.com/iphone-shipments-hit-record-855-million-fourth-quarter-2021
Margins: ~38% (not just 5nm): https://investor.tsmc.com/chinese/e...12fc3ba28169ec091a86/4Q21ManagementReport.pdf

Samsung:
Galaxy S22 as indicator of Samsung 4nm, there have been delays: https://www.tomsguide.com/news/samsung-galaxy-s22-delays-heres-the-ship-date-for-each-model-now
Margins: 34% (all semiconductor) https://news.samsung.com/global/samsung-electronics-announces-fourth-quarter-and-fy-2021-results
Thanks Fred, I'm only looking for yields.
 

fansink

Active member
Sorry Fred, if margins were released for each node, that would still be problematic in determining that nodes yield, but a single margin for all nodes is meaningless for determining a specific nodes yield.
 

Fred Chen

Moderator
Sorry Fred, if margins were released for each node, that would still be problematic in determining that nodes yield, but a single margin for all nodes is meaningless for determining a specific nodes yield.
Yes, we're only going to see the single margin for everything lumped together, since that probably looks nicer.

The yield is actually a fluctuating number, so I never take such reports seriously. What really matters is if they delivered so many millions to end users, and in doing so, could they have lost on margin. For example TSMC's 5nm diluted margins (by their own admission) for two years before they raised prices.
 

fansink

Active member
Maybe that's why rumor has it that Intel and Apple will be TSMC's two biggest costumers for N2?

The reason I believe that yields are important is that it’s a fairly straightforward metric for how a foundry’s node is progressing.

These yield data would allow time vs yield growth curves, which would be a valuable comparative tool.

The fact that such yield data is not released, and is well guarded, unless or until it is high enough to brag about, confirms its value.
 
Yield is a combo of design and process. In the design end, die size, corner simulation, and testing criterium will all change the yield dramatically. This is why the foundry cannot promise the yield for its customers. In some recent reports, Snapdragon 4 Gen 8 yields at 35%, and, at the same node, yields of Exynos are even much worse. So, the process is not the only factor.

If you are asking about the defect density of each node, then there are a few old threads in this blog you might find interesting [shorturl.at/hmrMS], [shorturl.at/cegAW].
 

fansink

Active member
Yield is a combo of design and process. In the design end, die size, corner simulation, and testing criterium will all change the yield dramatically. This is why the foundry cannot promise the yield for its customers. In some recent reports, Snapdragon 4 Gen 8 yields at 35%, and, at the same node, yields of Exynos are even much worse. So, the process is not the only factor.

If you are asking about the defect density of each node, then there are a few old threads in this blog you might find interesting [shorturl.at/hmrMS], [shorturl.at/cegAW].

Thank you so much James, obviously defect density is much better than yield, since it’s independent of die size. I do vaguely remember the defect density graphs, but at the time it did not make a sufficient impression, now it has, thanks to you.

I’m now looking for defect density for Intel, Samsung, and TSMC various nodes, and you have provided me with an excellent start.
 
Glad I can help. Indeed, it is very significant to learn the defect density of each company’s processes. If you find something conclusive, please share it with us.
 

Fred Chen

Moderator
It won't really help you directly estimate yield, but gives an idea of relatively how the companies are doing.

Intel: https://www.theverge.com/2022/1/26/22903138/intel-q4-2021-january-2022-earnings-best-year
30 million Tiger Lakes sold, margin over 50%

TSMC:
Using iPhone13 shipments as an indicator, obviously doing well: https://www.imore.com/iphone-shipments-hit-record-855-million-fourth-quarter-2021
Margins: ~38% (not just 5nm): https://investor.tsmc.com/chinese/e...12fc3ba28169ec091a86/4Q21ManagementReport.pdf

Samsung:
Galaxy S22 as indicator of Samsung 4nm, there have been delays: https://www.tomsguide.com/news/samsung-galaxy-s22-delays-heres-the-ship-date-for-each-model-now
Margins: 34% (all semiconductor) https://news.samsung.com/global/samsung-electronics-announces-fourth-quarter-and-fy-2021-results
The first Tiger Lake count was over a year old; more recently, it is now reported that over 100 million Tiger Lakes had shipped: https://www.hardwaretimes.com/intel..., Intel's,ramping notebook in Intel's history.

iPhone 12 (A14 launched around same time as Tiger Lake) had also crossed 100 million in 2021: https://www.notebookcheck.net/iPhone-12-unit-sales-crack-100-million-in-seven-months.548608.0.html

100 million is a good volume these days, but the smaller die sizes of the A14 and A15 make them easier to yield, and with fewer wafers, compared to the Tiger Lake (quad-core). Some Intel CPUs are more than 4 cores, and thus, even larger.

Moreover, a recent iPhone 13 examination indicates possibly that the 5nm design rules that were used were comparable to or looser than the published ones for Intel 7: https://semiwiki.com/forum/index.ph...-bionic-soc-n5p-details-from-unitedlex.15273/.

At least in the sampled location(s), the M0 pitch is >40 nm and fin pitch > 50 nm, which should help yield.
 

fansink

Active member
Glad I can help. Indeed, it is very significant to learn the defect density of each company’s processes. If you find something conclusive, please share it with us.
I will definitely share any relevant data I find, thanks again James.
 

fansink

Active member
The first Tiger Lake count was over a year old; more recently, it is now reported that over 100 million Tiger Lakes had shipped: https://www.hardwaretimes.com/intel-ceo-xeon-cpu-shipments-in-dec-exceeded-amds-yearly-epyc-sales-3nm-2nm-on-track-for-2023-2024/#:~:text=In the client segment, Intel's,ramping notebook in Intel's history.

iPhone 12 (A14 launched around same time as Tiger Lake) had also crossed 100 million in 2021: https://www.notebookcheck.net/iPhone-12-unit-sales-crack-100-million-in-seven-months.548608.0.html

100 million is a good volume these days, but the smaller die sizes of the A14 and A15 make them easier to yield, and with fewer wafers, compared to the Tiger Lake (quad-core). Some Intel CPUs are more than 4 cores, and thus, even larger.

Moreover, a recent iPhone 13 examination indicates possibly that the 5nm design rules that were used were comparable to or looser than the published ones for Intel 7: https://semiwiki.com/forum/index.ph...-bionic-soc-n5p-details-from-unitedlex.15273/.

At least in the sampled location(s), the M0 pitch is >40 nm and fin pitch > 50 nm, which should help yield.
Thank you Fred, it's alot of information to sift through,and may take me a while to translate into defect density. I will ping you with any further questions I may have.

One problem with Intel data is the added variable of binning.
 

Daniel Nenni

Admin
Staff member
I will definitely share any relevant data I find, thanks again James.

Defect density was a common metric for fabs to share but they don't do it anymore. When Intel went into the foundry business last time they used outdated TSMC slides to discredit them saying a Pure-play Foundry could not go where an IDM Foundry could, the old foundry business model was dead, etc... TSMC quit sharing yield data after that. The problem you have is yield data changes and a slow ramping process really is the semiconductor walk of shame.

The TSMC Symposium is coming up in June. It will be interesting to see what they present. TSMC did not allow media originally but they do now so the amount of information is a lot less. A sign of the times for sure.

Look at Tom Dillinger's past coverage of the TSMC Symposiums. He will be there with me this year as well.

 
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