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Let's investigate the A15 SoC extracted from the iPhone 13 Pro Max built with TSMC's one of most advanced process technologies (N5P).
unitedlex.com
"Key layout and process features observed include tight diffusion termination (e.g., unique single diffusion break), contact over the active gate (COAG), optimized gate cut after replacement metal gate (RMG) formation and PMOS with SiGe fins for high mobility channels (HMC). It's not much different from the first generation 5nm technology (N5). There seems to be some fine-tuning in each observed feature to claim a performance boost with N5P technology."
At least in the sampled location(s), the M0 pitch is not aggressive (>40 nm) while the gate pitch is close to 50 nm.
"In short, since N5P is a process in the N5 family (5nm node variants), the evolution from N5 to N5P doesn't seem to show a significantly altered process as described above. To find new ways to scale devices, major leading-edge device manufacturers are likely implementing different scaling optimization approaches within the same process node with the help of (DTCO), where the scaling booster is one of the parameters."
1. Fin layer (pitch ~52 nm in SRAM ~37 nm pitch in logic clip) is done by SAQP, as there are 3 etch depths.
2. Gate layer uses a cut mask.
3. If M0 includes 28 nm pitch (not shown here), then it must be done by SALELE (4-mask multipatterning: LELE + 2 cuts).
4. 50 nm gate pitch and 40 nm metal pitch would result in the contact center-to-center of 32 nm, which would also suggest at least double patterning for contacts, e.g., separation into gate and diffusion contacts.
Back to the M0 layer here - besides the pitch being surprisingly loose (~40 nm), if you take a look at the three central lines, there are two different linewidths, and the gaps between are also quite narrow, well under the Rayleigh resolution criterion (0.61*13.5/0.33=25 nm). If the dielectric spaces and metal lines fit a fixed pitch, it could be a single exposure, but that isn't what is seen here. It looks like LELE is done here. This does not yet include possible extra exposures for cutting lines.
For sure, the speculated 30 nm minimum metal pitch is not seen here, and even the fin pitches are way loose. There is no absolute requirement that minimum pitches should always be used.
30 nm pitch single exposure is easy to claim for long lines, but when you have shortened metal portions, they can be rounded out. No way to avoid line cuts here.
Fitting the line cut can be tricky too. These can also be hard to print, especially when under the Rayleigh resolution limit. This may be necessitated by the half-pitch of the next connecting metal layer.
Cuts can also exhibit stochastic appearances as well:
Also see the referred paper: W. Gao et al., "Patterning process exploration of metal 1 layer in 7nm node with 3D patterning flow simulations," Proc. SPIE 9426, 942606 (2015).
unitedlex.com