Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/tsmc-to-reduce-euv-layers-for-3nm-as-part-of-cip.14536/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020771
            [XFI] => 1050170
        )

    [wordpress] => /var/www/html
)

TSMC to reduce EUV layers for 3nm as part of CIP

Fred Chen

Moderator

As part of a Continuous Improvement Plan (CIP), TSMC will target reducing EUV machine use. From 25 EUV layers for 3nm down to 20, for example. Tool cost is one issue. Another is the heavy utility consumption (electric power, water), which is actually another specific type of cost.
 

Daniel Nenni

Admin
Staff member
TSMC N3 is 20+ EUV layers and Intel 4 is 6 EUV layers? How can that possibly be competitive in regards to PPA?
 

count

Active member
There will be a supply bottleneck at advanced nodes limited by EUV tooling, so if TSMC can get the number of layers down by 20% while still maintaining performance/quality, it means they could increase output/revenue in addition to reducing costs.
 

Fred Chen

Moderator
That's right, the limited supply of EUV tools on schedule would be their most pressing issue. It would drive more efficient multipatterning.
 

IanD

Active member
TSMC N3 is 20+ EUV layers and Intel 4 is 6 EUV layers? How can that possibly be competitive in regards to PPA?
If you believe Intel 4 will be 6 EUV layers, I've got a bridge you might want to buy. TSMC N5 is 15 EUV layers...

Unless Intel are redefining "layers" -- for example they say "1 metal layer" (Intel story) where TSMC say "3 EUV layers" (DP metal + via)...
 

count

Active member
If you believe Intel 4 will be 6 EUV layers, I've got a bridge you might want to buy. TSMC N5 is 15 EUV layers...

Unless Intel are redefining "layers" -- for example they say "1 metal layer" (Intel story) where TSMC say "3 EUV layers" (DP metal + via)...

Intel 4 is formally Intel 7nm right?

6 EUV layers may have been what Intel was originally planning for 7nm, but I think they have decided to increase the number of layers in Intel 4 from the original 7nm plans. That may explain the difference.
 

IanD

Active member
Intel 4 is formally Intel 7nm right?

6 EUV layers may have been what Intel was originally planning for 7nm, but I think they have decided to increase the number of layers in Intel 4 from the original 7nm plans. That may explain the difference.
If Intel 4 used to be Intel 7nm and has been renamed to be comparable with TSMC processes, then geometrically speaking (pitch, density) it presumably falls in between TSMC N5 (15 EUV masks/layers) and TSMC N3 (25 EUV masks/layers).

All the EUV layers are used for the bottom few critical fine-pitch layers (e.g. gate, MEOL, M0-M1-M2), increasing the number of metal layers doesn't affect this.

So I don't believe Intel 4 can only have 6 EUV layers, unless Intel use a different definition of "layer" to everyone else.
 

count

Active member
If Intel 4 used to be Intel 7nm and has been renamed to be comparable with TSMC processes, then geometrically speaking (pitch, density) it presumably falls in between TSMC N5 (15 EUV masks/layers) and TSMC N3 (25 EUV masks/layers).

All the EUV layers are used for the bottom few critical fine-pitch layers (e.g. gate, MEOL, M0-M1-M2), increasing the number of metal layers doesn't affect this.

So I don't believe Intel 4 can only have 6 EUV layers, unless Intel use a different definition of "layer" to everyone else.
I don't believe Intel 4 has 6 EUV layers either.

I think when Intel was planning Intel 7nm several years ago they were originally planning for a small number of EUV layers, but as recent reality sank in they realized that they needed to increase the number of EUV layers. I think the 6 EUV layer number that Daniel is referencing may be a several years old number.
 

IanD

Active member
I don't believe Intel 4 has 6 EUV layers either.

I think when Intel was planning Intel 7nm several years ago they were originally planning for a small number of EUV layers, but as recent reality sank in they realized that they needed to increase the number of EUV layers. I think the 6 EUV layer number that Daniel is referencing may be a several years old number.
That could be true, if they were doing this planning at the same time they were running headlong into their 10nm disaster by trying to avoid EUV and using quad (or even hex?) patterning, which is one reason for the multi-year delay -- basically, their approach didn't work. TSMCs approach with EUV (N7+ ==> N5 ==> N3) did work, I expect Intel will have to use a similar number of EUV layers at a given node if they want a process that can yield...
 

Fred Chen

Moderator
Last year at IRPS, Intel revealed after all the delay they didn't change anything for their 10nm process at that time (being used for Tiger Lake), except adding an upper metal layer, and making the MIM capacitor denser.

 

Paul2

Active member
There will be a supply bottleneck at advanced nodes limited by EUV tooling, so if TSMC can get the number of layers down by 20% while still maintaining performance/quality, it means they could increase output/revenue in addition to reducing costs.

For that they could rolled a separate "optimisation node" few month down the line rather than trimming a leading edge process.

Second, I believe 3N chips were in design for at least 3 years now. They cannot just yank 5 layers out of a sudden without updating PDK, and everything downstream.
 

IanD

Active member
For that they could rolled a separate "optimisation node" few month down the line rather than trimming a leading edge process.

Second, I believe 3N chips were in design for at least 3 years now. They cannot just yank 5 layers out of a sudden without updating PDK, and everything downstream.
It depends what they do. Some EUV layers are double patterned, as the source power and wafer throughput goes up they may be able to switch some of these to single patterned to reduce cost. Or the reduced-EUV cost-optimised process might be called N3+ or something else -- this is similar to what was done with N7==>N6 and N5==>N4
 

IanD

Active member
Last year at IRPS, Intel revealed after all the delay they didn't change anything for their 10nm process at that time (being used for Tiger Lake), except adding an upper metal layer, and making the MIM capacitor denser.

So the rumours that they had to ditch COAG and/or cobalt interconnect to get yield up were wrong? Did Intel mention either of these at IRPS?

Or by "original 10nm" are they comparing the 10nm+ process to the production 10nm process after these changes had already been made, not the "true original" 10nm process first launched which was a disaster?
 

Fred Chen

Moderator
So the rumours that they had to ditch COAG and/or cobalt interconnect to get yield up were wrong? Did Intel mention either of these at IRPS?

Or by "original 10nm" are they comparing the 10nm+ process to the production 10nm process after these changes had already been made, not the "true original" 10nm process first launched which was a disaster?
It's 10nm+ compared to the first version. The comparison was only the layer list and the MIM difference was mentioned. They did not show reliability comparison actually but presented the slew of reliability tests.
 

IanD

Active member
It's 10nm+ compared to the first version. The comparison was only the layer list and the MIM difference was mentioned. They did not show reliability comparison actually but presented the slew of reliability tests.
So according to Intel, removing COAG and/or cobalt interconnect is "no change" because the number of layers are the same?

How can you tell when an Intel PR guy is lying? His lips are moving....
 

Fred Chen

Moderator
So according to Intel, removing COAG and/or cobalt interconnect is "no change" because the number of layers are the same?

How can you tell when an Intel PR guy is lying? His lips are moving....
From the abstract:

We provide a comprehensive overview of the reliability characteristics of Intel’s 10+ logic technology. This is a 10 nm technology featuring the third generation of Intel’s FinFETs, seventh generation of strained silicon, fifth generation of high-k metal gate, multi-Vt options, contact over active gate, single-gate isolation, 14 metal layers, low-k inter-layer dielectric, multi-plate metal-insulator-metal capacitors, two thick-metal routing layers for low-resistance power routing, and lead-free packaging. The technology meets all relevant reliability metrics for certification.

From the introduction:

Intel’s 10+ process is an update to the previously described 10 nm process, featuring improved transistor performance, 14 metal layers (vs. 13 metal layers), and a higher-density multi-plate MIM capacitor.
 

Fred Chen

Moderator
Intel 10nm+ layers.png
 

IanD

Active member
OK, so COAG and cobalt are back -- if they ever went away...

The problem Intel have is they've spouted so much BS since 14nm about how wonderful their 10nm process is and how soon it will be ready -- or that it's in mass production when it patently isn't -- that nobody believes them any more even if they are telling the truth, and they've done the same with fiddled/biased CPU benchmarks. It's the boy who cried wolf...
 
Top