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TSMC’s U.S. Engineers Are “Babies” Say Taiwanese After The Former Leave For America

Daniel Nenni

Admin
Staff member
Wei is more MBA minded, and more American cultured, despite living in the US less than Chang, and not having a business school experience behind him. This is what was his undoing when Chang had to move in back to fix after the duo I believe.

At around first time Wei's first try as Co-CEO, he pushed for abstract "business performance" too much, while forgetting about what was happening on the ground (TSMCs 16nm-28nm train wreck,) leading to a mess-up a decade ago. Definitely a man who was conditioned to go after "new exciting things."

Not true at all. TSMC 28nm and 16nm were great nodes.

28nm was a big node for TSMC. TSMC followed Intel with the gate-last implementation and was the first foundry to 28nm. The others UMC, Samsung, Chartered, etc... did gate-first and did not yield. TSMC ended up with a record market share thanks to 28nm and that market share keeps growing.

The big problem with 16nm was the name. Intel and Samsung had 14nm and TSMC had to explain why 16nm different than 14nm. That name was chosen by Morris Chang as respect for Intel since their 14nm was more dense. Samsung called theirs 14nm even though it was comparable to TSMC 16nm. Now node names are mostly marketing and TSMC is playing that game quite well.

Morris Change leaving TSMC was a good thing, his time was past. I don't think you will find a TSMC employee that would disagree.
 

Paul2

Active member
Paul, can you expand on "TSMCs 16nm-28nm train wreck"?

They significantly lagged on their internal roadmap for new process integration. They did not remotely match Intel's density on their 16nm, and 10nm was even worse relatively speaking. The early jump on EUV was what pulled them out of the water.

Their yield improvement was also lagging significantly in comparison to how fast their previous nodes went.

2 different TSMC client team people would tell me that Wei made an impression of a somewhat nebulous American style executive who significantly distracted company focus on... well... god knows what during his first years as a co-CEO.

And they didn't mean TSMC's side ventures into power electronics, and solar, but an overall impression "some new random idea out of a business journal" coming from above every month.
 
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cliff

Member
They moved to double patterning, finfets, and routable contact layers. Huge benefits. These foundries have made mind-boggling progress.

Please expand on Intel's density on 16nm vs TSMC. Is one process geared for yield, the other for performance (oxide thickness, for example)? Gate pitch? Via spacing? M2 pitch? M4+ pitch? Please back up your statements.
 

Paul2

Active member
Please expand on Intel's density on 16nm vs TSMC. Is one process geared for yield, the other for performance (oxide thickness, for example)? Gate pitch? Via spacing? M2 pitch? M4+ pitch? Please back up your statements.

They had lower density for mainstream logic process. Their leakage at 16nm was not terrible, but Intel had better one with higher density for the high perf node.

Intel was not really into contract foundry when they got 14nm, but Samsung, and GloFo were still in business for the latest node, and TSMC's yield, and perf advantage was not obvious.

They moved to double patterning, finfets, and routable contact layers. Huge benefits. These foundries have made mind-boggling progress.

And so did Samsung+GloFo, which were, again, not far behind on yield, and performance. Nvidia was going with Samsung Foundry for a long time, and they dominated the market with chips fabbed at Samsung.

Anyways, TSMC has widened the gap again again by being 1-2 years ahead on the EUV. That bet made more than a decade ago paid off immensely.
 

nghanayem

Active member
They had lower density for mainstream logic process. Their leakage at 16nm was not terrible, but Intel had better one with higher density for the high perf node.

Intel was not really into contract foundry when they got 14nm, but Samsung, and GloFo were still in business for the latest node, and TSMC's yield, and perf advantage was not obvious.



And so did Samsung+GloFo, which were, again, not far behind on yield, and performance. Nvidia was going with Samsung Foundry for a long time, and they dominated the market with chips fabbed at Samsung.

Anyways, TSMC has widened the gap again again by being 1-2 years ahead on the EUV. That bet made more than a decade ago paid off immensely.
Small correction. Intel was the lead partner for EUV until 10nm started solidifying and Intel thought that it wouldn’t be production ready until the 2020s and they slowed down on their EUV research. When TSMC looked at the data they thought it would be good by the late 2010s. Intel lost this bet and by the time 10nm came out in a reasonable state apple was using N5 and the rest were on EUV optical shrinks of N7.

Other than that well said. It is my understanding that intel 14nm is more comparable to foundry 10nm (in ppa and even more complex design rule wise). As an interesting side note, it always amazed me how far intel could push its nodes over the years. Yeah 14nm density and power draw don’t hold a candle to what you could do on N7, but all of the process enhancements and relaxed dimensions on later iterations of 14nm allowed it be competitive on the performance front. It seems like similar magic is happening to 10nm as the 13900k can hit iso performance at like 40% the power despite being very similar to it’s predecessor (architecturally).

Also worth noting is that Samsung 14nm made it to market faster than N16.
 

nghanayem

Active member
What are densities on actual products? They could likely be much lower than advertised for the nodes.
This is highly product dependent (and not just on which libraries you use). An example of this is AMDs 6500xt which got what appears to be a plug and play upgrade to N6 with like a few percent shrink. Meanwhile the PS5 made full use of all DTCO opportunities to shrink it’s die size like 18% or something crazy like that. For this reason I don’t know what “real densities” to give you Fred.

Sorry I couldn’t give a more insightful answer, I’m not super proficient with this sort of thing given that I’m a chemical engineer.
 

nghanayem

Active member
Nghayanem might have gotten the numbers from here ... https://semiwiki.com/semiconductor-manufacturers/intel/6713-14nm-16nm-10nm-and-7nm-what-we-know-now" (Scotten Jones)

The Intel rules are tighter, but probably painful to pass the DRCs, correct? Is it worth it? Does TSMC make it easier for customers to get designs done?
Not this specific article, but similar conclusions are allover this site and the larger www.

As for the second point, rumor on the street is that 14nm was a real bear to design for. Shockingly I’ve even heard that it is worse than 10nm.
 

Fred Chen

Moderator
Nghayanem might have gotten the numbers from here ... https://semiwiki.com/semiconductor-manufacturers/intel/6713-14nm-16nm-10nm-and-7nm-what-we-know-now" (Scotten Jones)

The Intel rules are tighter, but probably painful to pass the DRCs, correct? Is it worth it? Does TSMC make it easier for customers to get designs done?
https://www.angstronomics.com/p/the-truth-of-tsmc-5nm
TSMC 5nm clip.png
 

cliff

Member
Great article. Thanks for pointing it out.
I have a working knowledge of GF and TSMC 12 and above, but know nothing on Intel and processes below 16-12nm. This gives me an idea of what to expect, but the poly pitch minimum isn't the most critical dimension within a geometry node IMO. Routability comparisons are probably more important than poly pitch. For example, we prefer a poly pitch of 96 vs 90 on TSMC 16, and a pitch of 84 vs 78 on GF. We create our own stdcells and P&R system. We don't pick minimum sizes. The decisions are based on routability more than absolute process minimums. Oh yea, make sure you chip doesn't melt. Sometimes a little space is a good thing.
 

hskuo

Active member
Small correction. Intel was the lead partner for EUV until 10nm started solidifying and Intel thought that it wouldn’t be production ready until the 2020s and they slowed down on their EUV research. When TSMC looked at the data they thought it would be good by the late 2010s. Intel lost this bet and by the time 10nm came out in a reasonable state apple was using N5 and the rest were on EUV optical shrinks of N7.

Other than that well said. It is my understanding that intel 14nm is more comparable to foundry 10nm (in ppa and even more complex design rule wise). As an interesting side note, it always amazed me how far intel could push its nodes over the years. Yeah 14nm density and power draw don’t hold a candle to what you could do on N7, but all of the process enhancements and relaxed dimensions on later iterations of 14nm allowed it be competitive on the performance front. It seems like similar magic is happening to 10nm as the 13900k can hit iso performance at like 40% the power despite being very similar to it’s predecessor (architecturally).

Also worth noting is that Samsung 14nm made it to market faster than N16.
If looking at how tsmc selected and migrated technologies from node to node, we would find tsmc usually takes steady small steps to secure success. For example, in 20nm to 16nm, there was almost only transistor architecture change with nearly the same DR. The transition becomes very successful from technology node's POV. We can expect the same mindset from 3nm to 2nm soon.
For EUV, there would be more stories. If we remembered, there were several alternative in advanced patterning besides EUV, like MEBDW, nanoimprint and others. tsmc lithography guru Burn Lin preferred MEBDW[1] for the concerns of powder shortage in Taiwan and spent most of his efforts trying to make MEBDW be production ready and be as successful as immersion lithography which he is recognized as the major technology contributor. Unfortunately, it was not successful and Burn Lin retired. In parallel, tsmc worked in EUV with ASML. I believed the news from IBM[2] was the triggered point to let tsmc management find EUV could be reaching production ready point. They duplicated the IBM practice and started to pour in hundreds of engineers to make EUV production ready with ASML for years. Eventually tsmc becomes the leader in EUV manufacturability. An excellent management team with successful execution records is important. The obedience culture could be another good ingredient of foundry success. tsmc have both of them now and no surprise of the success.

[1] MEBDW news in 2008: https://news.softpedia.com/news/TSMC-to-Install-MEBDW-Lithography-System-in-2009-97287.shtml
[2] EUV production breakthrough news in 2014: https://www.eetimes.com/ibm-breaks-euv-throughput-record/
 
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nghanayem

Active member
If looking at how tsmc selected and migrated technologies from node to node, we would find tsmc usually takes steady small steps to secure success. For example, in 20nm to 16nm, there was almost only transistor architecture change with nearly the same DR. The transition becomes very successful from technology node's POV. We can expect the same mindset from 3nm to 2nm soon.
For EUV, there would be more stories. If we remembered, there were several alternative in advanced patterning besides EUV, like MEBDW, nanoimprint and others. tsmc lithography guru Burn Lin preferred MEBDW[1] for the concerns of powder shortage in Taiwan and spent most of his efforts trying to make MEBDW be production ready and be as successful as immersion lithography which he is recognized as the major technology contributor. Unfortunately, it was not successful and Burn Lin retired. In parallel, tsmc worked in EUV with ASML. I believed the news from IBM[2] was the triggered point to let tsmc management find EUV could be reaching production ready point. They duplicated the IBM practice and started to pour in hundreds of engineers to make EUV production ready with ASML for years. Eventually tsmc becomes the leader in EUV manufacturability. An excellent management team with successful execution records is important. The obedience culture could be another good ingredient of foundry success. tsmc have both of them now and no surprise of the success.

[1] MEBDW news in 2008: https://news.softpedia.com/news/TSMC-to-Install-MEBDW-Lithography-System-in-2009-97287.shtml
[2] EUV production breakthrough news in 2014: https://www.eetimes.com/ibm-breaks-euv-throughput-record/
Haven’t heard of mebdw before. Thanks for giving me some more reading material!

Looking at the timeframe. I would have to agree that 2014 is probably when TSMC looked at euv and locked it in for N5 with a tentative merge during the lifetime of N7. Given 10nm was supposed to come out in like 2017 or 2018, this breakthrough was likely too late for intel to merge euv into 10nm. However looking back at old articles from that time I remember seeing that intel was still flip floping on if they should minimize EUV usage for 7nm or embrace it (which I find interesting given the choices that Samsung and TSMC made).

As for TSMC’s execution, management, and risk management engines no-one can take that away from them. They are masters of that craft (to say nothing of the chip making craft ;) ).
 

Daniel Nenni

Admin
Staff member
If looking at how tsmc selected and migrated technologies from node to node, we would find tsmc usually takes steady small steps to secure success. For example, in 20nm to 16nm, there was almost only transistor architecture change with nearly the same DR. The transition becomes very successful from technology node's POV. We can expect the same mindset from 3nm to 2nm soon.
For EUV, there would be more stories. If we remembered, there were several alternative in advanced patterning besides EUV, like MEBDW, nanoimprint and others. tsmc lithography guru Burn Lin preferred MEBDW[1] for the concerns of powder shortage in Taiwan and spent most of his efforts trying to make MEBDW be production ready and be as successful as immersion lithography which he is recognized as the major technology contributor. Unfortunately, it was not successful and Burn Lin retired. In parallel, tsmc worked in EUV with ASML. I believed the news from IBM[2] was the triggered point to let tsmc management find EUV could be reaching production ready point. They duplicated the IBM practice and started to pour in hundreds of engineers to make EUV production ready with ASML for years. Eventually tsmc becomes the leader in EUV manufacturability. An excellent management team with successful execution records is important. The obedience culture could be another good ingredient of foundry success. tsmc have both of them now and no surprise of the success.

[1] MEBDW news in 2008: https://news.softpedia.com/news/TSMC-to-Install-MEBDW-Lithography-System-in-2009-97287.shtml
[2] EUV production breakthrough news in 2014: https://www.eetimes.com/ibm-breaks-euv-throughput-record/

TSMC started taking smaller process steps to accommodate Apple which started at 20nm (iPhone6) when Apple first came to TSMC. The first version of 16nm (20nm plus FinFETs) was not good so Apple designed to Samsung 14nm (iPhone 6+). TSMC then revised 16nm and had engineers "help" Apple migrate the Samsung 14nm design to 16nm so the iPhone 6+ was split between Apple and TSMC. Customers did not like this of course so there was the "chipgate" fiasco which is the last time Apple split SoCs amongst foundries.

This new half step yield learning process methodology allowed TSMC to pass Intel. Now Intel is doing the same with 4 and 3, 20A and 18A, which is quite smart.

Yes TSMC 10nm was not a good node since it was not a big performance or power boost from 16/12nm so most companies skipped it, except of course Apple. Most companies skipped 20nm as well due to the success of TSMC 28nm. Same can be said for TSMC 7+ (the first EUV node).

A lot of this has to do with design challenges (EDA and IP). 20nm was the first double patterning node so it was a layout challenge. 7+ was the first EUV node design challenge. Cost is also a factor when moving to a new process. There has to be a clear ROI to move designs from one node to another (power, performance, area, price)

Which brings us to GAA. Again, another design challenge and the cost increase will be significant compared to N3x so many companies will skip the first N2 version, my opinion.
 

cliff

Member
Daniel, that was a great explanation of how the we have gotten to this point and answered a lot of questions. I hope to one day work in the land of giants, but for now I can only help the poor souls who can afford sub $3M NRE ASICs, so I will ask the same question again that I asked in the past...

Now that TSMC has perfected the 16/12 recipe, what is the likelihood of TSMC creating that 16nm recipe in Arizona? Will that be an only Taiwan-China-Japan process, else I will be forced to second source at US companies who don't call you back.
 
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