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Transistor count calculation problem

techcossack

New member
Hi all,

Recently I’ve come across an issue - is there a formula to calculate transistor count on various technology nodes? I know that nodes like 5nm 7nm etc are mostly marketing terms from TSMC etc, and that they no longer accurately reflect gate length or metal pitch, but how do industry experts manage to remember the transistor counts on all these technology nodes without consulting some kind of reference table?
Thanks!
 

dl324

Member
Not likely. The industry experts get the data from the fab.

Transistor density is calculated using memory cells that are allowed to use tighter design rules than other logic because the structures are very regular and they can optimize algorithms for postprocessing the data to make features more manufacturable.

If you have access to the memory cell rules you can do test layouts to see the highest density you can achieve and know that if particular rules could be tighter, manufacturing might have been able to accommodate closer spacings for particular topologies by altering backend data processing.
 

Daniel Payne

Moderator
Hi all,

Recently I’ve come across an issue - is there a formula to calculate transistor count on various technology nodes? I know that nodes like 5nm 7nm etc are mostly marketing terms from TSMC etc, and that they no longer accurately reflect gate length or metal pitch, but how do industry experts manage to remember the transistor counts on all these technology nodes without consulting some kind of reference table?
Thanks!
Some chip design companies openly state what their total transistor count is, so it's mostly bragging rights, and they often round to the nearest billion transistors for the largest SoC designs. In the early days of ASICs and FPGA designs, the companies would often cite Gate count, where a Gate was typically a 2 input NAND gate, containing four transistors per gate. An SoC with mostly SRAM or DRAM content will have the highest density of transistors per unit area, because of how memory cells are designed. In general, the larger the die, the larger the number of transistors, but the lower the yield. The smaller the die, the smaller the number of transistors, and the higher the yield. Most chip design teams choose a particular process node, based on feature size, transistor density, yields, performance, IP libraries, and cost.
 

Xebec

Active member
Slightly related -- a new website has a (slightly sensationalist sounding) article referring to a reverse engineering effort from Systemplus that estimates N5 at ~ 134 MT/mm2. If I'm understanding the article, it explains that manufacturers have some leeway in choosing which point on their optimization/performance curves for sizing they want. The article also indicates that ASML's own estimate for 5nm is far too dense ("over 180MT/mm2"). The article doesn't challenge any actual other performance metrics of N5 than density. There's also an appeal to authority in the article..


I'm curious if this would influence the range of 130-230 MT/mm2 as posited on wikichip?
 

Scotten Jones

Moderator
Slightly related -- a new website has a (slightly sensationalist sounding) article referring to a reverse engineering effort from Systemplus that estimates N5 at ~ 134 MT/mm2. If I'm understanding the article, it explains that manufacturers have some leeway in choosing which point on their optimization/performance curves for sizing they want. The article also indicates that ASML's own estimate for 5nm is far too dense ("over 180MT/mm2"). The article doesn't challenge any actual other performance metrics of N5 than density. There's also an appeal to authority in the article..


I'm curious if this would influence the range of 130-230 MT/mm2 as posited on wikichip?
You are mixing up and trying to compare two completely different ways of measuring density.

If you want to compare processes to each other you can't base it on designs because designer decisions can dramatically change density even on the same process. I have written about the problem here: https://semiwiki.com/semiconductor-manufacturers/tsmc/285856-effect-of-design-on-transistor-density/

I would also like to point out that TechInsights analyzed TSMC 5nm a long time ago and I have had actual measured values for that process from TechInsights and other sources for a long time. That article doesn't have anything new in it. ASML's estimate is for a specific size of cell and is correct for that particular case.
 

Xebec

Active member
You are mixing up and trying to compare two completely different ways of measuring density.

If you want to compare processes to each other you can't base it on designs because designer decisions can dramatically change density even on the same process. I have written about the problem here: https://semiwiki.com/semiconductor-manufacturers/tsmc/285856-effect-of-design-on-transistor-density/

I would also like to point out that TechInsights analyzed TSMC 5nm a long time ago and I have had actual measured values for that process from TechInsights and other sources for a long time. That article doesn't have anything new in it. ASML's estimate is for a specific size of cell and is correct for that particular case.
Got it - that makes sense. I'm here to learn so I appreciate the explanation Thanks Scotten!
 
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