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The Technology Gap Between Leading Western and Chinese Semiconductor Foundries

Daniel Nenni

Admin
Staff member
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China's chip industry is experiencing a remarkable growth spurt. But how well do we truly understand the breathtaking pace at which Chinese manufacturers like SMIC and Huahong are closing the gap with their Western rivals? Here's a visual comparison of semiconductor technology development by market leaders such as IBM, Motorola Solutions, Intel Corporation and TSMC since 1978. The chart contrasts their progress with the achievements of Chinese companies.

The semiconductor industry in China faced a widening technological gap, reaching 17 years by 2014. This year marked a turning point, as China's State Council identified the semiconductor industry as critical to national security in its "Outline for Advancing the National Integrated Circuit Industry". The launch of the national "Big Fund" and the "Made in China 2025" initiative one year later provided resources and direction for Chinese companies to begin (very) successfully closing the gap.

Building on a similar plot published by Center for Security and Emerging Technology (CSET) already in 2021, I verified and corrected release dates for some technology nodes, incorporated the latest global forecasts for sub-3nm nodes, and updated the progress of Chinese CMOS foundries in 14-nm and 7-nm.

Here's the exciting part! Here are my predictions for the Chinese chipmaking sector. I strongly believe that China, particularly Huawei, might still be well-positioned to announce a new 5-nm chip fabricated entirely by SMIC, as its manufacturing could require utilization of tools the Chinese chipmakers already have. However, achieving high-volume production at a profitable level might be challenging due to the process complexity associated with using older-generation deep ultraviolet lithography (DUVL) tools. In fact, the same challenge applies to the recently announced Kirin 9000s chip, designed by Hisilicon and manufactured entirely in China.

As, in my opinion, we (Western nations) are about to lose the battle for mature node (14-nm and older) production, the only thing that undeniably hinders China's progress in developing state-of-the-art CMOS nodes (3-nm and beyond) is the U.S. embargo on advanced extreme ultraviolet lithography (EUVL) equipment exports from ASML (Netherlands) and Canon Inc. (Japan). My current estimates suggest that China currently lags behind the leader in developing advanced lithography tools by about 15 years. In this case, catching up could take even longer, potentially 20 years or more. However, Chinese companies are rapidly closing the gap (5-10 years) in other segments of the advanced chip-making value chain, including design software, wafer processing tools, and packaging technologies. Only time will tell how China navigates these challenges. Perhaps SSMB-EUV technology, developed by the brilliant minds at Tsinghua University, could offer a potential remedy.

Author: Michał Bochenek
 
The real question is whether China can pursue this objective while simultaneously dealing with it’s huge housing overhang that continues be a hidden slow motion disaster, while also avoiding overproduction and dumping in the other sectors it has invested heavily in over the past 10 years (EVs, batteries, solar, semis). Seems like the central and local governments are good at initiating coordinated industrial policy, but not very good at managing supply, demand or profitability.

China Has a Plan for Its Housing Crisis. Here’s Why It’s Not Enough.​

A new approach by China’s top leaders is bold but pales against the problem: a vast number of empty apartments no one wants to buy.

And every action has negative reactions.

‘It Is Desolate’: China’s Glut of Unused Car Factories​

Manufacturers like BYD, Tesla and Li Auto are cutting prices to move their electric cars. For gasoline-powered vehicles, the surplus of factories is even worse.


When do the chickens come home to roost with so many misplaced investments ?
 
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‘It Is Desolate’: China’s Glut of Unused Car Factories
Manufacturers like BYD, Tesla and Li Auto are cutting prices to move their electric cars. For gasoline-powered vehicles, the surplus of factories is even worse.


When do the chickens come home to roost with so many misplaced investments ?

The Chinese housing crisis is crazy on so many levels; something ugly has to happen here.

However, it’s too early to call the ‘Chinese EV bubble’ catastrophic yet — There are a lot of Chinese manufacturers of EVs, so they could just be in the standard ‘consolidation phase’ that happens when you have too many medium+ sized manufacturers of a product.

The Chinese have a serious tech and cost advantage in EVs because of their arrangement and extended investment in LFP battery chemistry. There is a long story here too but short version is when the tech was ‘made viable’ in Canada, a series of moves made it so it would cost a royalty if you developed/build the tech in western nations, but China was able to get it for essentially free (and legally this time). The Chinese continued developing the tech, and only now (2024-2025) do the LFP patents / royalty restrictions expire, but it’s the West that’s a decade+ behind.

So when there is some kind of collapse of the Chinese car industry, whatever emerges could be a (more) serious force to be reckoned with. Their cars are already taking away significant sales from legacy automakers in the EU.
 
It would be fun to plot a version of this chart to include Taiwan and the US. Though challenging because it seems extremely variable between when companies indicate ‘we’ve hit mass production’ and when you can actually buy products.
 
View attachment 1943

China's chip industry is experiencing a remarkable growth spurt. But how well do we truly understand the breathtaking pace at which Chinese manufacturers like SMIC and Huahong are closing the gap with their Western rivals? Here's a visual comparison of semiconductor technology development by market leaders such as IBM, Motorola Solutions, Intel Corporation and TSMC since 1978. The chart contrasts their progress with the achievements of Chinese companies.

The semiconductor industry in China faced a widening technological gap, reaching 17 years by 2014. This year marked a turning point, as China's State Council identified the semiconductor industry as critical to national security in its "Outline for Advancing the National Integrated Circuit Industry". The launch of the national "Big Fund" and the "Made in China 2025" initiative one year later provided resources and direction for Chinese companies to begin (very) successfully closing the gap.

Building on a similar plot published by Center for Security and Emerging Technology (CSET) already in 2021, I verified and corrected release dates for some technology nodes, incorporated the latest global forecasts for sub-3nm nodes, and updated the progress of Chinese CMOS foundries in 14-nm and 7-nm.

Here's the exciting part! Here are my predictions for the Chinese chipmaking sector. I strongly believe that China, particularly Huawei, might still be well-positioned to announce a new 5-nm chip fabricated entirely by SMIC, as its manufacturing could require utilization of tools the Chinese chipmakers already have. However, achieving high-volume production at a profitable level might be challenging due to the process complexity associated with using older-generation deep ultraviolet lithography (DUVL) tools. In fact, the same challenge applies to the recently announced Kirin 9000s chip, designed by Hisilicon and manufactured entirely in China.

As, in my opinion, we (Western nations) are about to lose the battle for mature node (14-nm and older) production, the only thing that undeniably hinders China's progress in developing state-of-the-art CMOS nodes (3-nm and beyond) is the U.S. embargo on advanced extreme ultraviolet lithography (EUVL) equipment exports from ASML (Netherlands) and Canon Inc. (Japan). My current estimates suggest that China currently lags behind the leader in developing advanced lithography tools by about 15 years. In this case, catching up could take even longer, potentially 20 years or more. However, Chinese companies are rapidly closing the gap (5-10 years) in other segments of the advanced chip-making value chain, including design software, wafer processing tools, and packaging technologies. Only time will tell how China navigates these challenges. Perhaps SSMB-EUV technology, developed by the brilliant minds at Tsinghua University, could offer a potential remedy.

Michał Bochenek
Great chart, but a normalized cost/wafer at each node would be revealing. The Chinese government appears to be pursuing more advanced nodes regardless of cost, which would never fly in a market economy. It takes a subsidized one. The cost of the Chinese strategy to be an adversary of western capitalistic countries must be huge - in the trillions of dollars per year at the GNP level, considering limited markets, technology exclusion, and reduced foreign investment.

(Side comment: I grew up in a time when the US government promoted a "duck and cover" campaign in US schools, to protect yourself from nuclear attacks. So silly. We had civil defense drills, complete with sirens going off. Yet the world seems like a more dangerous place now than then. One difference between then and now, the most likely scenarios for disaster back then were due to mistakes. Now the most likely disaster scenarios are due to strategies.)
 
The Chinese housing crisis is crazy on so many levels; something ugly has to happen here.

However, it’s too early to call the ‘Chinese EV bubble’ catastrophic yet — There are a lot of Chinese manufacturers of EVs, so they could just be in the standard ‘consolidation phase’ that happens when you have too many medium+ sized manufacturers of a product.

So when there is some kind of collapse of the Chinese car industry, whatever emerges could be a (more) serious force to be reckoned with. Their cars are already taking away significant sales from legacy automakers in the EU.

I agree - there will be a few 3-4 superpower Chinese EV brands after consolidation, but in the meantime, the economics are ugly for the local governments that put land and lots of money into losing gasoline-powered (ICE) automobile and EV companies. The US had fewer than 70 auto plants in the 1970s when imports hollowed out the US manufacturing business. China has over 100 ICE plants alone, and demand has dropped by 69%. That’s like losing an entire US auto industry in just a few years. Who pays the price for that ? Local workers, local governments. We only see the pain from the outside indirectly - reduced domestic demand within China and deflation.
 
His graph has 3nm at 2035? It's definitely much sooner since it would be more of an incremental change from 5nm (still quadruple patterning), rather than 7nm to 5nm (double to quadruple patterning). For 3nm, the big change would be more via masks (if not self-aligned) per layer, but that would also be true for the EUV case (because of sub-35 nm via center-to-center pitches).
 
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Great chart, but a normalized cost/wafer at each node would be revealing. The Chinese government appears to be pursuing more advanced nodes regardless of cost, which would never fly in a market economy. It takes a subsidized one.

Isn't that exactly what the US government is doing right now? Pursuing domestic production of many things regardless of cost, through various subsidy program (CHIPS act, IRA, Biosecure Act etc, ) which would never fly in a market economy
 
Isn't that exactly what the US government is doing right now? Pursuing domestic production of many things regardless of cost, through various subsidy program (CHIPS act, IRA, Biosecure Act etc, ) which would never fly in a market economy
With the CHIPS Act, it is not the equivalent, it's just a subsidy to build fabs, not operate them, or subsidize production. With the Inflation Reduction Act and the part of the Act regarding the solar energy supply chain, yes, it is comparable. IMO, it'll fail. The BIOSECURE Act is not a law, and probably won't be.
 
With the CHIPS Act, it is not the equivalent, it's just a subsidy to build fabs, not operate them, or subsidize production. With the Inflation Reduction Act and the part of the Act regarding the solar energy supply chain, yes, it is comparable. IMO, it'll fail. The BIOSECURE Act is not a law, and probably won't be.

If chips made in the US are 30% more expensive than that of Taiwan,then why should fabless companies buy from US fabs rather than TW fabs?Unless the US government subsidize US production,or force companies to buy from US fabs (which is a form of indirect subsidy)
 
If chips made in the US are 30% more expensive than that of Taiwan,then why should fabless companies buy from US fabs rather than TW fabs?Unless the US government subsidize US production,or force companies to buy from US fabs (which is a form of indirect subsidy)
First of all, @Scotten Jones , who does very impressive analyses in my opinion, thinks the cost difference to TSMC is only 7% per wafer higher in AZ than in Taiwan. The most important factor in the cost difference, by Scotten's analysis, is that TSMC decided to build smaller fabs in the US than in Taiwan, which is in his excellent article:


On the other hand, construction costs and taxes in the US are definitely higher than in Taiwan, so if the US does want domestic fabs we're going to have to subsidize construction and state and local property and capital equipment taxes. Labor is not a big factor in cost per wafer.
 
View attachment 1943

China's chip industry is experiencing a remarkable growth spurt. But how well do we truly understand the breathtaking pace at which Chinese manufacturers like SMIC and Huahong are closing the gap with their Western rivals? Here's a visual comparison of semiconductor technology development by market leaders such as IBM, Motorola Solutions, Intel Corporation and TSMC since 1978. The chart contrasts their progress with the achievements of Chinese companies.

The semiconductor industry in China faced a widening technological gap, reaching 17 years by 2014. This year marked a turning point, as China's State Council identified the semiconductor industry as critical to national security in its "Outline for Advancing the National Integrated Circuit Industry". The launch of the national "Big Fund" and the "Made in China 2025" initiative one year later provided resources and direction for Chinese companies to begin (very) successfully closing the gap.

Building on a similar plot published by Center for Security and Emerging Technology (CSET) already in 2021, I verified and corrected release dates for some technology nodes, incorporated the latest global forecasts for sub-3nm nodes, and updated the progress of Chinese CMOS foundries in 14-nm and 7-nm.

Here's the exciting part! Here are my predictions for the Chinese chipmaking sector. I strongly believe that China, particularly Huawei, might still be well-positioned to announce a new 5-nm chip fabricated entirely by SMIC, as its manufacturing could require utilization of tools the Chinese chipmakers already have. However, achieving high-volume production at a profitable level might be challenging due to the process complexity associated with using older-generation deep ultraviolet lithography (DUVL) tools. In fact, the same challenge applies to the recently announced Kirin 9000s chip, designed by Hisilicon and manufactured entirely in China.

As, in my opinion, we (Western nations) are about to lose the battle for mature node (14-nm and older) production, the only thing that undeniably hinders China's progress in developing state-of-the-art CMOS nodes (3-nm and beyond) is the U.S. embargo on advanced extreme ultraviolet lithography (EUVL) equipment exports from ASML (Netherlands) and Canon Inc. (Japan). My current estimates suggest that China currently lags behind the leader in developing advanced lithography tools by about 15 years. In this case, catching up could take even longer, potentially 20 years or more. However, Chinese companies are rapidly closing the gap (5-10 years) in other segments of the advanced chip-making value chain, including design software, wafer processing tools, and packaging technologies. Only time will tell how China navigates these challenges. Perhaps SSMB-EUV technology, developed by the brilliant minds at Tsinghua University, could offer a potential remedy.

Michał Bochenek

I hope the author can provide any evidence that there were only 2 to 5 or 6 years of gaps in semiconductor manufacturing between PRC and the West from 1975 until early 1980s.

The 10 years of "Cultural Revolution" ended in October 1976. The whole PRC's education system, research institutions, and industry were ruined and trying to recover from CCP's brutal and crazy exercises for those 10 years and beyond. It's impossible to have just 2 years of gaps between PRC and the West back then.
 
His graph has 3nm at 2035? It's definitely much sooner since it would be more of an incremental change from 5nm (still quadruple patterning), rather than 7nm to 5nm (double to quadruple patterning). For 3nm, the big change would be more via masks (if not self-aligned) per layer, but that would also be true for the EUV case (because of sub-35 nm via center-to-center pitches).
Fred's comment regarding Chinese 3nm timing and via patterning challenge is accurate, and this has also been realized by Chinese researchers in one recent SPIE paper:“BEOL and MOL patterning & metallization are the main bottleneck modules of advanced-node IC manufacturing. EUVL not only significantly enhances their pattern density, but also helps to shrink the CD of small vias/contacts/cuts/blocks with relaxed pitches. Of course, there exist other non-optical shrinking techniques such as chemical (e.g., RELACS) and thermo-mechanical (e.g., SAFIER) shrinking, spacer/polymerassisted narrowing, etching controlled top-down tapering, and cross-bar pillar/hole patterning.“

I would think DUV based BEOL metal pitch scaling is no more an extremely difficult issue. First, the existing SAQP(4x) process allows DUVL to be extended to ~20nm pitch (about 2-3nm logic node), and their proposed SASP (7x) can push it to ~12nm metal pitch (14-10A logic node). If you look at the SASP process complexity, it's not that bad and yield may be lower but acceptable (of course, NOT for very large scale manufacturing such as Apple iPhone or Intel PC, but enough for high-performance computing such as company AI applications). The remaining challenge is small vias/contacts/cuts/blocks patterning, but there are many ways to shrink CD of small features (NOT pitch) as mentioned above. Namely, if SAVB technique can be incorporated into SAQP as proposed in the paper, it would NOT be a huge jump or 15y gap when moving to 3nm (i.e., 22-23nm metal pitch, printable by SAQP). The bigger challenge is beyond 3nm node wherein they proposed to switch to SASP based SAVC process, but it won't take that long.
 

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It is easy for China to close the technology gap, just bomb Taiwan and wipe TSMC out.
If you can't catch up, drag your competitor down instead.
 
As, in my opinion, we (Western nations) are about to lose the battle for mature node (14-nm and older) production, the only thing that undeniably hinders China's progress in developing state-of-the-art CMOS nodes (3-nm and beyond) is the U.S. embargo
Sole big buyers of fancy chips are wealthy Western companies. Any other point doesn't worth the talk, unless that one is solved.
 
Fred's comment regarding Chinese 3nm timing and via patterning challenge is accurate, and this has also been realized by Chinese researchers in one recent SPIE paper:“BEOL and MOL patterning & metallization are the main bottleneck modules of advanced-node IC manufacturing. EUVL not only significantly enhances their pattern density, but also helps to shrink the CD of small vias/contacts/cuts/blocks with relaxed pitches. Of course, there exist other non-optical shrinking techniques such as chemical (e.g., RELACS) and thermo-mechanical (e.g., SAFIER) shrinking, spacer/polymerassisted narrowing, etching controlled top-down tapering, and cross-bar pillar/hole patterning.“

I would think DUV based BEOL metal pitch scaling is no more an extremely difficult issue. First, the existing SAQP(4x) process allows DUVL to be extended to ~20nm pitch (about 2-3nm logic node), and their proposed SASP (7x) can push it to ~12nm metal pitch (14-10A logic node). If you look at the SASP process complexity, it's not that bad and yield may be lower but acceptable (of course, NOT for very large scale manufacturing such as Apple iPhone or Intel PC, but enough for high-performance computing such as company AI applications). The remaining challenge is small vias/contacts/cuts/blocks patterning, but there are many ways to shrink CD of small features (NOT pitch) as mentioned above. Namely, if SAVB technique can be incorporated into SAQP as proposed in the paper, it would NOT be a huge jump or 15y gap when moving to 3nm (i.e., 22-23nm metal pitch, printable by SAQP). The bigger challenge is beyond 3nm node wherein they proposed to switch to SASP based SAVC process, but it won't take that long.
It's nice to see they are investigating alternative approaches to EUV. We need more options. Competition is good for all.
 
With the CHIPS Act, it is not the equivalent, it's just a subsidy to build fabs, not operate them, or subsidize production. With the Inflation Reduction Act and the part of the Act regarding the solar energy supply chain, yes, it is comparable. IMO, it'll fail. The BIOSECURE Act is not a law, and probably won't be.
It's not a subsidy to operate fabs or subsidise production *yet*. Just wait for the sunk cost fallacy to kick in.
 
Interesting... I wish the impact could be quantified better than an "introduction date". Perhaps a more interesting metric would be time to reach a certain volume (50K wafers?) or yield?
 
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