Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/spie-2021-virtual-advanced-lithography-conference-euv-throughput-at-28-nm-minimum-pitch.13807/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2020470
            [XFI] => 1040170
        )

    [wordpress] => /var/www/html
)

SPIE 2021 (virtual) Advanced Lithography conference: EUV throughput at 28 nm minimum pitch

Fred Chen

Moderator
This year's SPIE Advanced Lithography conference was held virtually due to the COVID impact on travel. While papers are now immediately available, you can get stuck waiting, from the web traffic. Also, many papers were video only.

There were a number of papers of course on probably the hottest topic, EUV. By piecing together information from some key papers, you can get some important information.

It is already worth noting that several papers focused on single exposure at the 28 nm pitch. This is no coincidence, as Samsung's 4nm foundry node and TSMC's 5 nm node have been reported to sport such a minimum metal pitch (see here: https://semiwiki.com/forum/index.ph...-for-the-foreseeable-future.13730/#post-45732).

The first piece of information is the throughput, presented in paper 11609-3: High-NA EUV Llthography exposure tool: key advantages and program progress by J. van Schoot et al.
SPIE 2021 ASML EUV tool throughput update.png

With the field power level at 250 W, this graph can be converted to throughput vs dose:
SPIE 2021 ASML EUV tool throughput vs dose update.png

Another presentation by ASML, paper 11609-6, 0.33 NA EUV systems for high-volume manufacturing, by E. Verhoeven et al., showed the availability averaging to ~85%, so we may get wafers per day by 0.85*WPH*24, which is shown below for the 0.33 NA case only.
1614267055949.png

On the graph, the doses and corresponding WPD are noted for the 14 nm lines and spaces (L/S) case and the 20 nm hp contact hole (C/H) cases. The contact hole cases are addressed in the high-NA paper 11609-3. The 28 nm half-pitch (hp) C/H dose can be halved to produce the same width as the 20 nm hp C/H (single exposure dose is 80 mJ/cm2, for addressing stochastic defects), and two such exposures can be interleaved in double patterning to go from 28 nm hp to 20 nm hp.
20 nm vs 28 nm hp contact.png

The 14 nm hp L/S case is discussed in more detail in paper 11609-29, Extending 0.33 NA EUVL to 28 nm pitch using alternative mask and controlled aberrations, by D. Rio et al., which indicated that the best illumination for 28 nm pitch with conventional EUV masks only used 50% of the source power, so 250 W is effectively halved to 125 W. An attenuated phase shift mask would need to be developed to use the full 250 W. Incidentally, negative resist exposure of the areas outside the metal line locations is recommended by several papers at the conference, including 11609-29.

The best reported cases of throughput are >2000 wafers per day (in paper 11609-6). It becomes clear that 20 nm hp contact holes as well as 28 nm pitch lines and spaces are too slow as single exposures to support this reported throughput. So double patterning must be used to get the higher throughput at the larger (1.4x for C/H, 2x for L/S) pitch, with either the full source power (for L/S) or the lower dose (for C/H).
 

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  • 0.33 NA WPD vs dose.png
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Daniel Nenni

Admin
Staff member
Are memory makers using EUV in production today or just starting? And at what geometry? 10nm?

 

hskuo

Member
Are memory makers using EUV in production today or just starting? And at what geometry? 10nm?

Samsung is leading EUV adoption in DRAM 1z nodes. You can find answer here.
 

Fred Chen

Moderator
Are memory makers using EUV in production today or just starting? And at what geometry? 10nm?

Only Samsung has publicly announced the use of EUV and SK Hynix announced the plans to use it.

DRAM has a regular and predictable cell layout, so cell features have benefited from self-aligned patterning. There are still layers which use double patterning.
 

Fred Chen

Moderator
Wonder if the EUV masks in different notes are taken into considerations to estimate the throughput (wpd)?
A 30 nm pitch single exposure would be slower than the 40 nm or 60 nm pitch single exposure. But the 60 nm pitch can be double exposed to get the 30 nm pitch. But to preserve the availability, need an extra tool to catch the second pass from the first.
 
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james juang

New member
A 30 nm pitch single exposure would be slower than the 40 nm or 60 nm pitch single exposure. But the 60 nm pitch can be double exposed to get the 30 nm pitch. But to preserve the availability, need an extra tool to catch the second pass from the first.
Can we estimate how many EUV machines will be installed in TSMC AZ from the average throughput?
 

Fred Chen

Moderator
Can we estimate how many EUV machines will be installed in TSMC AZ from the average throughput?
If we use the 1250 wpd, that's 37500 wafers per month, so if we want 150,000 wafers per month, that needs 4 tools per layer (mask). At TSMC's 5nm, there are 15 layers (masks) assumed, so 60 tools would be needed, more than TSMC or any particular company would have at the moment.
 

IanD

Active member
If we use the 1250 wpd, that's 37500 wafers per month, so if we want 150,000 wafers per month, that needs 4 tools per layer (mask). At TSMC's 5nm, there are 15 layers (masks) assumed, so 60 tools would be needed, more than TSMC or any particular company would have at the moment.
There might be 15 EUV layers but only a few (e.g. gate/MEOL) are ultra-fine pitch and need either double patterning or longer exposure times. If this wasn't the case TSMC wouldn't be able to ship the 5nm volumes that they are doing.
 

Fred Chen

Moderator
There might be 15 EUV layers but only a few (e.g. gate/MEOL) are ultra-fine pitch and need either double patterning or longer exposure times. If this wasn't the case TSMC wouldn't be able to ship the 5nm volumes that they are doing.
If TSMC currently has 30 tools, it could support 75,000 wafers per month at this rate, plus 37,500 wafers per month for every 15 tools added.
 
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