Intel 18A "too good" but design lags

[IanD]

Based on reading (and re-reading) the contents of this thread and the outstanding information being discussed, I can completely see why TSMC would take the less technically aggressive, and more business flexible solution over Intel's 18A direction.

The effort in moving designs from one node to the next is a really big deal for foundry customers. The ability to service a wide spectrum of different customer designs is also a key metric that a foundry-as-a-service company needs to be very cognitive of.

I am now wondering about the business viability of the less flexible 18A process vs TSMC's N2, then A16, then A14 approach? All of these processes (including 18A) are more expensive than big military equipment (and we are talking about full submarines here. Pretty much everything but an aircraft carrier!). I would hate to get something like this wrong.

As far as the raw silicon technology is concerned TSMCs BSPD approach is more advanced than Intel's, they bring the power up directly under the transistors. They can presumably accept the added risk (or cost?) because A16 is a "premium" follow-on process to N2, so there's a fallback option for customers if there are any problems -- also a good reason for using compatible libraries between N2 and A16 for your first use of BSPD in mass production.

Intel have put all their eggs in the 18A BSPD-only basket, so maybe chose a slightly safer approach for the vias, they can afford any small area overhead from this because their BSPD-only libraries save a lot of area compared to TSMCs FSPD-compatible ones. If they pull all this off (including high yield and low cost in mass production) then they'll have a very good solution, but it's risky for both Intel and customers -- if they have any major problems like the ones that killed their 10nm process (and almost killed some customers for it...) and delayed it for years, there's no quick/easy way back for customers (no FSPD process option, libraries not compatible with FSPD) and Intel Foundry is dead... :-(

I guess it's the difference between a customer-driven company (TSMC) where failing to deliver customer-critical devices is not really an option so you only do one big new thing at a time, and a technology-driven one like Intel who will aggressively push everything to the limit (and accept higher wafer costs and lower yields) and sometimes fail -- which works (well, mostly...) if you're an IDM selling super-high-margin CPUs, if your new product is delayed you carry on selling the existing ones or even back-port the new design to the old process.

Maybe Intel had no choice other than to do this and take the risk to try and catch up with TSMC, but if I was an 18A customer I wouldn't be sitting comfortably... ;-)

 

[OneEng]

As far as the raw silicon technology is concerned TSMCs BSPD approach is more advanced than Intel's, they bring the power up directly under the transistors. They can presumably accept the added risk (or cost?) because A16 is a "premium" follow-on process to N2, so there's a fallback option for customers if there are any problems -- also a good reason for using compatible libraries between N2 and A16 for your first use of BSPD in mass production.

Intel have put all their eggs in the 18A BSPD-only basket, so maybe chose a slightly safer approach for the vias, they can afford any small area overhead from this because their BSPD-only libraries save a lot of area compared to TSMCs FSPD-compatible ones. If they pull all this off (including high yield and low cost in mass production) then they'll have a very good solution, but it's risky for both Intel and customers -- if they have any major problems like the ones that killed their 10nm process (and almost killed some customers for it...) and delayed it for years, there's no quick/easy way back for customers (no FSPD process option, libraries not compatible with FSPD) and Intel Foundry is dead... :-(

I guess it's the difference between a customer-driven company (TSMC) where failing to deliver customer-critical devices is not really an option so you only do one big new thing at a time, and a technology-driven one like Intel who will aggressively push everything to the limit (and accept higher wafer costs and lower yields) and sometimes fail -- which works (well, mostly...) if you're an IDM selling super-high-margin CPUs, if your new product is delayed you carry on selling the existing ones or even back-port the new design to the old process.

Maybe Intel had no choice other than to do this and take the risk to try and catch up with TSMC, but if I was an 18A customer I wouldn't be sitting comfortably... ;-)

Thanks for the clarification.

I suspect that Pat G put together the 5NI4Y plan with all "home-run-timing" and that lots of emphasis is being placed on 18A actually being significantly superior to TSMC's processes in base metrics.

Where I believe Pat G (and Intel as a company) has missed the boat is in the fundamentals.

For quite some time I have advocated that "Services" are "Products" and should be treated with standard product management practices. Who is your buying persona? What is your user stories? What is your market position? SWOT analysis? Competitive analysis?

Intel doesn't appear to understand how to become a good supplier for a service product. This is my biggest concern for Intel's turn-around.

 

[lefty]

I'm a bit confused. If backside power is optional on A16, what exactly is the difference between A16 without backside power and N2?

 

[jorgequinonez]

I'm a bit confused. If backside power is optional on A16, what exactly is the difference between A16 without backside power and N2?

I thought that A16 = (N2 + BSPD). So I'm confused too.

 

[OneEng]

I believe that what Ian is saying (at least how I understand it), is that the libraries for N2 and A16 are compatible. As a result, A16 isn't as optimal as 18A in density.

 

[tooLongInEDA]

Thanks for the clarification.

I suspect that Pat G put together the 5NI4Y plan with all "home-run-timing" and that lots of emphasis is being placed on 18A actually being significantly superior to TSMC's processes in base metrics.

Where I believe Pat G (and Intel as a company) has missed the boat is in the fundamentals.

For quite some time I have advocated that "Services" are "Products" and should be treated with standard product management practices. Who is your buying persona? What is your user stories? What is your market position? SWOT analysis? Competitive analysis?

Intel doesn't appear to understand how to become a good supplier for a service product. This is my biggest concern for Intel's turn-around.

I like your way of looking at this and think that definitely applies to a foundry business (and likely even more so to EDA tools).

But surely the chip (device) business too ?

When you consider some of the products Intel's been selling these surely have a large services and support element. I assume that when you engage with MobilEye that you're not just buying one or more devices - you'll need everything that comes with that (eval boards, software, lots of AE support, etc) to easily design this into your product. This applies to lots of Intel products. And it's hardly new. Intel also has history in software through Wind River and McAfee. So I can't believe that large parts of Intel don't do this. I guess it never fully bridged the chasm over to the fab group in the past. The dangers of being so internally focused for so long.

 

[Fred Chen]

I just read Naga Chandrasekaran saying that 18A still had defect density challenges and milestones to achieve. https://seekingalpha.com/article/47...lobal-technology-and-ai-conference-transcript

 

[Artificer60]

I just read Naga Chandrasekaran saying that 18A still had defect density challenges and milestones to achieve. https://seekingalpha.com/article/47...lobal-technology-and-ai-conference-transcript

I believe that should be expected. He said that the process is basically sorted out, which leaves 4-6 months to get the yields up before they start cranking out volume for an EOY launch. For the first half of the year Naga indicated that the focus is on closing those gaps and providing engineering samples. While good yields are always desirable, you don't necessarily need them to provide a few samples to customers for preliminary evaluation.

 

[ChrisGar]

"Regarding the product side, I don't think the margins for server, desktop, and laptop CPUs will return to previous levels, even if Intel regains process leadership. AMD has become a significant competitor in both performance and volume."

I've wondered how Intel would do the financials if they split foundry & product -- and report gross margins for each.

For example -- let's say they have a product where total gross margins are 50%. If they report foundry/product separate financials -- then maybe each can report 25% gross margins. (which is not good based on industry numbers for either category)

 

[OneEng]

I believe that should be expected. He said that the process is basically sorted out, which leaves 4-6 months to get the yields up before they start cranking out volume for an EOY launch. For the first half of the year Naga indicated that the focus is on closing those gaps and providing engineering samples. While good yields are always desirable, you don't necessarily need them to provide a few samples to customers for preliminary evaluation.

I thought that Intel's Clearwater Forest was planned to be in HVM in Q3 (according to Intel roadmaps). Engineering samples seems doable, but HVM?

Additionally, I thought Qualcomm had a HVM product on 18A for October 2025?

 

[OneEng]

"Regarding the product side, I don't think the margins for server, desktop, and laptop CPUs will return to previous levels, even if Intel regains process leadership. AMD has become a significant competitor in both performance and volume."

I've wondered how Intel would do the financials if they split foundry & product -- and report gross margins for each.

For example -- let's say they have a product where total gross margins are 50%. If they report foundry/product separate financials -- then maybe each can report 25% gross margins. (which is not good based on industry numbers for either category)

It depends on which one they decide to sacrifice .

I have thought for some time that the exponentially increasing cost of new nodes was going to have an over-sized effect on the entire leading edge chip industry which has become accustomed to quickly improving performance and power over the last 3 decades.

 

[Artificer60]

I thought that Intel's Clearwater Forest was planned to be in HVM in Q3 (according to Intel roadmaps). Engineering samples seems doable, but HVM?

Additionally, I thought Qualcomm had a HVM product on 18A for October 2025?

Q3 is 6-9 months away. If 18A is still having significant issues in 6 to 9 months, the Intel is toast.

In HVM doesn't mean being shipped to customers. A product goes into HVM well before product launch. A couple of quarters in HVM before product launch is not unusual to build up initial inventory.

 

[OneEng]

Q3 is 6-9 months away. If 18A is still having significant issues in 6 to 9 months, the Intel is toast.

In HVM doesn't mean being shipped to customers. A product goes into HVM well before product launch. A couple of quarters in HVM before product launch is not unusual to build up initial inventory.

Intel said they planned Panther Lake in "mid 2025". So either that statement was overly optimistic, or the 18A yields are low for where they need to be to support Panther Lake. Correct?

 

[siliconbruh999]

Intel said they planned Panther Lake in "mid 2025". So either that statement was overly optimistic, or the 18A yields are low for where they need to be to support Panther Lake. Correct?

The initial ramp is in Oregon like always first batch is from there after they yield is sufficiently well it will be transferred to Arizona in H2 for true HVM

 

[MKWVentures]

Intel said they planned Panther Lake in "mid 2025". So either that statement was overly optimistic, or the 18A yields are low for where they need to be to support Panther Lake. Correct?

Naga and David gave the correct answer per actual internal timelines. 18A yields are low as expected for ALL new technologies and will increase over the next 12 months.

 

[Artificer60]

I think "yield" is one of the key paradigm shifts for Intel needs to internalize. What is considered acceptable yield for a CPU is different from what is considered acceptable for, say a cell phone chip. For their CPU business Intel could fuse off a bad processor and still sell the die as a lower category CPU (i.e. i3, i5, i7). Alternatively, if the die was on the slow end for speed, they could do the same thing. This ability to bin dice within the wafer has given Intel a lot more flexibility to tolerate lower yields than many of TSMCs customers can tolerate. Intel makes more profit at higher yields, but they still make some profit at yields that would be too low for some other products because of the ability to bin their processors.

I think this is part of what Naga drove Intel's thinking when he was referring to the "no wafer left behind" mindset that needs to change. I also believe this historical view of yield inherent in decades of experience for Intel veterans (like Gelsinger) colors their view of what is good and acceptable yield. It's not just a matter of learning to look at things in a new way. It is also a matter of unlearning the old ways of looking at things.

 

[Artificer60]

Naga and David gave the correct answer per actual internal timelines. 18A yields are low as expected for ALL new technologies and will increase over the next 12 months.

I would agree that most of the improvement should happen over the next 12 months for yield, but the need to drive down cost will go on much longer, since 18A is intended to be a long life foundry node. That will be a new space for Intel to operate in as traditionally their process life had a short tail and the benefit of driving improvement became progressively less over time.

 

[IanD]

I believe that what Ian is saying (at least how I understand it), is that the libraries for N2 and A16 are compatible. As a result, A16 isn't as optimal as 18A in density.

I believe that's the case, going by what was said in an earlier post (I've only seen N2 libraries) -- the N2 and A16 library cells are the same (same height and number of tracks), the difference is that with N2 you then define a conventional power mesh above them which competes for space with the signal interconnect, with A16 you define a backside power mesh below them which doesn't.

So the gains with A16 are lower power mesh voltage drop (a little bit higher speed), and density increase (also a bit more speed since average routing length is shorter) because there's no topside power mesh -- so the area savings with A16 depend directly on the power grid density which would be used in N2, which is why TSMC recommend it for "HPC-type" devices with high clock rates/power density and a dense power grid.

(also "actively cooled" because self-heating is worse, so the die has to be kept cooler)

It means that you can in theory switch a digital design relatively easily from N2 to A16 (or vice versa) using the same cell libraries, without a complete re-synthesis with new logic libraries which 18A would need -- only the back-end part of the design flow changes where routing capacitance/resistance and dynamic power drops are taken into account.

The PPA gains are not as high as a pure "BSPD-only" process like 18A, but the risk is lower -- you could go with A16 but revert to N2 if there are problems, or start with N2 and switch to A16 if the advantages become important and all is going well with it. There are always risks with a big technology jump and many customers are not willing to take the risk of an unproven "bleeding-edge" process, because this has come unstuck in the past -- see Intel 10nm, where cobalt interconnect and COAG turned out to be problematic... :-(

 

[MKWVentures]

The PPA gains are not as high as a pure "BSPD-only" process like 18A, but the risk is lower -- you could go with A16 but revert to N2 if there are problems, or start with N2 and switch to A16 if the advantages become important and all is going well with it. There are always risks with a big technology jump and many customers are not willing to take the risk of an unproven "bleeding-edge" process, because this has come unstuck in the past -- see Intel 10nm, where cobalt interconnect and COAG turned out to be problematic... :-(

How much time does it take to do a redesign and qualification between A16 and N2 or 18A and 14A.
Also what is the cost increase for BSPD vs PPA improvement. What is the ROI?

 

[IanD]

How much time does it take to do a redesign and qualification between A16 and N2 or 18A and 14A.
Also what is the cost increase for BSPD vs PPA improvement. What is the ROI?

That's a "how long is a piece of string?" question... ;-)

Any redesign/port takes a lot of time and effort and money, which will be considerably smaller if the libraries/processes are compatible.

The second one is a commercial question, you'd need to ask TSMC. Could be positive, could be negative -- you have to balance off cost, yield, consequences of delayed TTM and many other things...

What is certain is that having FSPD and BSPD processes with compatible libraries (like TSMC) reduces risk but also delivers less density improvement than Intel's BSPD-only approach.

The risk of going with Intel 18A is that if they screw up -- like happened with 10nm, ask Nokia -- and can't yield the process, your product is dead and there's no way back apart from throwing it in the bin and starting again (with TSMC?).

Which probably means completely missing your market window and not having a product at all. And unlike an IDM selling your own CPUs, you can't say "Never mind, just buy our previous-generation part, we'll give you a good deal"... :-(

That's not a good scenario for risk management in most people's minds, which is why Intel Foundry has been struggling to find customers and TSMC hasn't...