From what I have heard Intel 18A is somewhere between TSMC N3X and N2 in regards to PDK evaluations. I'm sure PPT slides will state it differently.
Shockingly, intel and TSMC seem to have shockingly consistent messaging on the matter:
TSMC's comment that N3P wouldn't be better than 18A, but that N2 would definitely would be the "most advanced process when it comes out"
Got this from X but too interesting to let it go by: "The design service and design enablement is still fairly weak at Intel right now, but the technology is just way too good." He noted Samsung's MOL had issues, but no comments on TSMC.
semiwiki.com
After thinking about the nebulous chart and intel's comment that they are comparing to "the most advanced non intel process available at the time". I think that the first symbol might be comparing to N3P and the second might be comparing to N2? Even if it is only comparing to N3P, I think it still tells the same story of better than N3-anything doesn't quite match up to N2 but with a 3-5Q TTM lead.
Intel hits their 2021 called shot of "unquestioned power-performance leadership in 2025", and seemingly even unquestioned PPA leadership in 2025. Meanwhile, TSMC strikes back in 2026 when the first N2 chips become commercially available. Then for our third feature film, "Return of the LTD" 14A and A16 duke it out. Given the partial BSPDN implementation on A16, it is hard to imagine how 14A doesn't once again seize the leadership position without it actually being less than a 10% area reduction.
With that said, there is still plenty of time for intel and TSMC to sling mud at each other on data light PPT slides or with CEO comments.
Nice details for ISSCC 2025 TSMC N2 vs 18A
View attachment 2498
How did they thought of putting inverse details one is presenting density one is presenting SRAM size
For reference, intel says their intel 4 6T SRAM was 0.024 um^2 (14.3% density boost for 18A). The 18A value is also the same as the reported/measured SRAM bitcell for N3E and the measured SRAM bitcell on A17-pro.
Wondering if the TSMC SRAM is a complete SRAM with interconnect and decoders / sense amps vs Intel only highlighting the base cell size ? If it's just the reciprocal, Intel comes to 47.6Mb/mm^2.
They are not inversely proportional. As you guessed, TSMC is talking about the whole kit and caboodle (as the SRAM density boost is likely more modest without the logic/design enhancements TSMC did on N2).
According to this graph, Intel has been the industry leader in advanced packaging since at least the Intel 7 node. However, it is unclear which packaging technologies Intel is referring to or comparing against.
From a volume perspective, I wouldn't be shocked if you told me they are the industry leader. Think of all of those Altera FPGAs, SPR, EMR, GNR, SRF, PVC, MTL, ARL, and LNLs. Intel said they were on track for what, like, 50-60M AI PCs in 2024? Let's call it maybe 10-20M Xeons with advanced packaging (since the low core count SPR/EMR are monolithic) and 5M FPGAs. I have a hard time imagining that NVIDIA AI chip + AMD AI chip + the MAX versions of Apple's Mx line + AMD's V-cache derivatives of their mainstream CPUs is much bigger (if it even is bigger) than 65-85M units per year. And that is assuming that all of that advanced packaging is being down on COWS/SOIC. I have to assume that a decent chunk of those 2.5D chips (everything that isn't the V-cache stuff) is being multi-sourced with OSATs as AMKOR and ASE group all have COWOS equivalents. Heck, I think I remember seeing ASE talk about how their 2.5D silicon interposer is drop in compatible with COWOS.
As for technology, as I said before, I think it is more nuanced than intel or TSMC let on. For 2.5D I think intel is clearly ahead. The silicon bridge approach is scalable to even larger package sizes and lower cost than the full size base die approach of COWOS. With EMIB your limit for how big you can go is practically just what your packaging substrate can handle. Considering TSMC is pushing their silicon bridge derivative of COWOS as the future and NVIDIA blackwell is using bridges instead of large base dies, TSMC seems to agree that the EMIB approach is simply superior. As for the 3D logic on logic stacking stuff, while intel was doing active base die fovros before SOIC was a thing, it is undeniable that TSMC has pulled ahead. V-cache launched in 2022 and only in 2025 is intel finally catching up by scaling from 45 solder bonds -> 9 micron Cu hybrid bonding and offering a more advanced base die in intel 3-T/3-PT that competes nicely with N5 base dies rather than a low density process like 22FFL/i16. To add insult to injury, if memory serves, TSMC is supposed to go from 9 -> 3 micron around then. So TSMC's lead on logic on logic stacking seems secure for the foreseeable future.
Intel claims they have best in class advanced package sort/test, know good die pre-assembly, and best in industry assembly yields as differentiation. But I am nowhere near qualified enough to say if that claim holds any water. Seems plausible I suppose if they got PVC out. To this day, I don't think there is any chip anywhere near as complex as that (and for good reason
), and I think it will be a long time until we see another chip that tops that on sheer absurdity.
TLDR I think intel could argue they are the leader, but I wouldn't call it "unquestioned". What is for sure indisputable, is that intel has
a leadership position in advanced packaging (emthesis on the
a).
Besides Amazon and Intel itself, are there any other customers utilizing Intel's advanced packaging?
Yes. At this point, I think intel has signed like 8 nonpublic advanced assembly/test customers. If memory serves, they said they were about to start production for one or maybe two (can't remember) new 2.5D customer recently (but I could be wrong and this could be wrong). There were also rumors last year that NVIDIA is dual sourcing H100 assembly with intel.
