Intel 18A tapeout without High-NA EUV

[Mooredaddy]

After all this time, including time spent with TSMC over 3nm, Intel 18A will not have lower minimum metal pitch than Intel 4.

Direct print EUV patterning of tight pitch metal layers for Intel 18A process technology node

This paper describes the direct print Extreme Ultra Violet (EUV) technology used for lithographic patterning of 30-36 nm pitch metal layers of Intel 18A technology node. Direct print EUV delivers cost effective pitch scaling to enable flexible design rules and ease of use for layout designers...

www.spiedigitallibrary.org

So is it just an optical shrink? Excuse my ignorance. What are some performance inferences one can make from this?

 

[nghanayem]

So is it just an optical shrink? Excuse my ignorance. What are some performance inferences one can make from this?

Maybe of just the transistors. Metal pitch can't change though, and with it the "easiest" way to increase density (as metal pitch is one of the things that determines std cell size). Performance wise there is a lot that can be changed without a density improvement. For 14nm intel was able to get like a 20% improvement at iso leakage from skl to cml. Same deal with intel 7 vs 10nm superfin. In fact from 10nm+ to 10nm superfin, and from the 14nm of kbl on the densities were even relaxed to give even more performance.

Long story short there are always ways to eek out some extra performance/lower leakage from better process control, refinements of the metal stack, ect.

 

[Mooredaddy]

Maybe of just the transistors. Metal pitch can't change though, and with it the "easiest" way to increase density (as metal pitch is one of the things that determines std cell size). Performance wise there is a lot that can be changed without a density improvement. For 14nm intel was able to get like a 20% improvement at iso leakage from skl to cml. Same deal with intel 7 vs 10nm superfin. In fact from 10nm+ to 10nm superfin, and from the 14nm of kbl on the densities were even relaxed to give even more performance.

Long story short there are always ways to eek out some extra performance/lower leakage from better process control, refinements of the metal stack, ect.

What is TSMC due to have out when 18A comes to market? It is my understanding N2 will be a yield learning node with a what appears to be a very modest density improvement over N3E due to it being TSMC’s first implementation of GAA. Is whatever the successor is to N2 going to be TSMC’s competitive offering to 18A?

 

[nghanayem]

What is TSMC due to have out when 18A comes to market? It is my understanding N2 will be a yield learning node with a what appears to be a very modest density improvement over N3E due to it being TSMC’s first implementation of GAA. Is whatever the successor is to N2 going to be TSMC’s competitive offering to 18A?

18A should enter HVM around when or a little bit before N2 enters HVM. There is also the period of Apple exclusivity. Whereas 20A is the learning node for 18A, in theory allowing for 18A to be ready for the masses. I could/hope to be wrong, but I think people might need to accept that until CFET becomes a thing density improvements might plument. We've already been seeing the slowdown for years, but N3, i4, and 2GAP might be the last hefty density boosts we see for a little while. I don't know for sure, but given how expensive EUV quad patterning would be, and the throughput problems that Fred pointed out high NA could cause I wouldn't be shocked if we can't get much smaller without having ballooning costs. If costs go too high the demand will lower to the point that new nodes can't be justified. Of course this is assuming the semi industry doesn't find a cheat (and eventually they always do).

 

[cliff]

Can anybody provide the metal 5 and 6 pitch, and the via45, via56 pitch, and the via5 to metal5 pitch?

 

[nghanayem]

Can anybody provide the metal 5 and 6 pitch, and the via45, via56 pitch, and the via5 to metal5 pitch?

From the horse's mouth, intel 4 is:

I suppose another benefit to not shrinking metal pitches is not needing any new metallurgies (yet).

 

[cliff]

WOW. Nice stack! Thank you.

 

[nghanayem]

WOW. Nice stack! Thank you.

Via pitches weren't in the briefing, but out of curiosity why would they matter? Doesn't the metal pitch tell you all you would need to know as a designer?

Also courtesy of AnandTech's coverage of the intel 4 brief

 

[cliff]

You caught me! I was trying to calculate the pitch. It is vary complex. The via spacing and the via to metal spacing is probably the top 2 variables, but there are a lot more. You've got end of line rules, illegal zone rules, and many many others. It took us over a man year to finalize the GF and TSMC 16-12nm pitch, but a lot of that was because we create our own standard cells and place and route system. There are a ton of trade-offs. Even if you gave me the entire DRM, it would take me a month minimum to calculate the pitch. I was just curious. 28nm was so much easier.

We almost never go with minimum standard cell height on our own standard cells. Customers can use the foundry supplied cells, but they are typically so small that running P&R at 100% utilization is never done, or at least I have never heard of it.