Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/chisel-hardware-construction-language-from-uc-berkeley.6979/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Chisel - Hardware Construction Language from UC Berkeley

Daniel Payne

Moderator
The students at UC Berkeley have some new Open Source software called Chisel used as a hardware construction language.

Just added Chisel to the Open Source tools list here.
 
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This is the best demonstration of the potential of chisel: rex computing , a cpu startup is talking about building chips(using chisel) with 10x better perf/power :

"“When Intel does this, they have 300 or more people on many teams over 18 months. We’re doing it with five on a tight schedule,”[1]


[1]http://www.nextplatform.com/2015/07/22/supercomputer-chip-startup-scores-funding-darpa-contract/
 
I liked this part:

“It takes 4200 picojoules to move 64 bits from DRAM to registers while it only takes 100 picojoules to do a double-precision floating point operation. It’s over 40x more energy to move the data than to actually operate on it. What most people would assume is that most of that 4200 picojoules is being used in going off-chip, but in reality, about 60% of that energy usage is being consumed by the on-chip cache hierarchy because of all of the extra gates and wires on the chip that the electrons go through. We are removing that 60%.”
 
I'm not so sure about how a 28nm CPU in 2016 is going to change the computing world, it sounds more like a proof of concept for yet another ISA.
 
Daniel - it seems this is the key value prop:

The compiler understands where data will need to be at different points and it inserts it where it should go instead of leaving it in DRAM and letting the chip’s memory management units fetch it when it needs to in an inefficient big handful—and with data included that likely will not be used anyway

Of course no saying it will be successful. Getting DARPA funding is probably not a good indicator of near-term fame and fortune, but the approach is an interesting twist on current expectations that the hardware has to figure out how to optimize memory accesses.
 
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Daniel, patience. it might take some time. But let's say they do have a great technology. Do you really see a realistic path for 14/20nm chip as the first chip in the current VC environment ?
 
Daniel, this might also be relevant to your list[1], allowing non experts to develop stuff like full wifi radios, rapidly.

[1]http://research.microsoft.com/en-us/projects/ziria/
 
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