Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/ballpark-semiconductor-economics-questions-re-tsmc-arizona-fab.15919/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Ballpark semiconductor economics questions re: TSMC Arizona Fab

jms_embedded

Active member
So TSMC is constructing its first Arizona fab with a planned output of 20K wafers per month using its 5nm process. There's room at this site for 5 more fabs in the future. The $12 billion number in TSMC's announcement is total spending on this project (the AZ site) from 2021 to 2029, presumably including more fabs. Scotten Jones posted an initial estimate for this 20K wpm fab of $5.4 billion.

Thought experiment: (very hypothetical)

It's December 2022 and the chip shortage is still painful. TSMC is doing so well that they decide they will construct a second fab with another 20K wpm at this site.

Choice 1: another 5nm fab, presumably about the same price.
Choice 2: a 40nm fab because there is a huge shortage of 40nm wafer capacity (again this is very hypothetical)

Questions, looking for very rough estimates:
- For choice 2, how much would it cost them to build it as a percentage of 5nm fab cost? I am assuming it would be less expensive because it's not EUV and 40nm is a much older node. (10% as much? 80% as much?)

- For choice 2, with today's prices what's the rough difference in cost per wafer they charge for 5nm vs. 40nm at high volumes (say at least 5% of total fab output)? is it more like 5:1 or 2:1 or 1.2:1 ?

- How "competitive" is choice 2 if "competitive" is defined as the ratio of this new fab's costs to other TSMC fabs with the same process?

I'm guessing choice 1 is fairly competitive, maybe 1.1 - 1.3x as high as other TSMC 5nm fabs given lower wpm and US location.

What about choice 2? 2x as high as other TSMC 40nm fabs? 10x?

----

Intent of thought experiment: My intuition tells me it doesn't make sense to build a new 40nm fab for two reasons:

1. given the site costs, they can earn more profit at this site with 5nm than with 40nm (costs more to build but higher return)

2. 40nm will be less competitive than 5nm because existing 40nm fabs have already been depreciated so their operating cost is much lower than a new 40nm fab.

But I was wondering if it's just slightly less sensible or completely bonkers to build a new 40nm fab.

(For the purposes of this question, ignore expectations of the foolishness of adding new 40nm capacity and the foolishness of foundry customers asking for capacity at 40nm instead of smaller nodes; assume that the demand is there.)
 
You already answered your own question -- it's the second reason, 40nm is dirt cheap because the fabs have been depreciated, so a new 40nm fab cannot possibly be cost-competitive.
Well just because I think something is true doesn't mean it is. :)

And how "dirt cheap" is 40nm because of depreciation?

I guess what I'm wondering is what happens if the world becomes desperate for 40nm parts? How much would it take to motivate more 40nm foundry capacity? Is the economics such that prices would have to rise by 10% to make it profitable, or rise by 100%?

TSMC was motivated to start building a 28nm fab in Japan (w/ Sony JV):

-----

TAIPEI (Taiwan News) — A subsidiary of Taiwan Semiconductor Manufacturing Co. (TSMC) said Tuesday (April 19) it will begin construction for a new chip plant in Japan's Kumamoto Prefecture on Thursday (April 21).

The chip fab is being built through a joint-venture between TSMC, Sony Semiconductor Solutions Corporation (SSS), and Denso called Japan Advanced Semiconductor Manufacturing Inc. (JASM). JASM and the Japanese government will invest a total of US$8.6 billion (NT$252 billion) into the project.

The new chip facility is being built in an industrial sector in the town of Kikuyo, according to Kyodo News. JASM said commercial production is slated to begin in December 2024.

The facility will have two production lines, one that produces 12 and 16 nanometer semiconductors, and one that will manufacture 22 and 28 nm ones. The plant will have a monthly capacity of 55,000 12-inch wafers.

The Kumamoto plant is expected to produce chips used in image sensors and microcontrollers. TSMC previously said the fab should create around 1,700 jobs.
 
Last edited:
"dirt cheap" means several times cheaper than a new build fab, not tens of percent. Once the cost of the fab building and equipment have been paid off, the remaining costs (maintenance, supplies, labour, power, water...) are a fraction of the costs when new -- the exact numbers vary from node to node, but I guess at least 2x cheaper, maybe even more -- I'm sure Scotten Jones has data on this ;-)

Which means a wafer price rise of at least 100% would be needed to make a new 40nm fab profitable, maybe even more...
 
Remember, TSMC 40nm is GDS compatible to GF, UMC, and SMIC so there is significant price pressure here. The TSMC business strategy is to push customers to process nodes that are not GDS compatible (IE FinFETs).

We currently have a mature node demand/supply imbalance. I do not see that continuing so building mature node fabs does not seem like a good investment unless it is funded by other sources like the Japan fabs. 28nm is also the last stand of CMOS so that process will live a VERY long life, absolutely.
 
Remember, TSMC 40nm is GDS compatible to GF, UMC, and SMIC so there is significant price pressure here. The TSMC business strategy is to push customers to process nodes that are not GDS compatible (IE FinFETs).

We currently have a mature node demand/supply imbalance. I do not see that continuing so building mature node fabs does not seem like a good investment unless it is funded by other sources like the Japan fabs. 28nm is also the last stand of CMOS so that process will live a VERY long life, absolutely.
two questions since I'm not that familiar with chip design:

- what does "GDS compatible" mean? is this digital circuitry only, or would analog designs also have mobility/compatibility between foundries?
- "28 nm is also the last stand of CMOS" -- did I miss something? I thought the smaller nodes (5nm etc.) were also based on CMOS. What's special about 28nm?

I don't know that I agree with the mature node supply/demand imbalance working out on its own... but I don't have any evidence to support that, other than pointing to projections of automotive electronics / IoT growth. On the other hand, TI is bumping up capacity in 300mm fabs (4 of them! Three new ones in Texas + refurbishing the Micron/IM Flash fab in Lehi, UT for 65nm + 45nm) so that should help; they appear to have become tired of relying on foundries so much and have taken matters into their own hands. Maybe that + a general trend of migrations to smaller nodes will free up enough capacity in the 300mm >28nm category.
 
The Fab shell TSMC is building in Arizona is a lot bigger than they need for 20k wpm, my expectation is they would be to ramp it up above 20k wpm before they build another shell. TSMC always builds extra clean room space.
 
two questions since I'm not that familiar with chip design:

- what does "GDS compatible" mean? is this digital circuitry only, or would analog designs also have mobility/compatibility between foundries?
- "28 nm is also the last stand of CMOS" -- did I miss something? I thought the smaller nodes (5nm etc.) were also based on CMOS. What's special about 28nm?

I don't know that I agree with the mature node supply/demand imbalance working out on its own... but I don't have any evidence to support that, other than pointing to projections of automotive electronics / IoT growth. On the other hand, TI is bumping up capacity in 300mm fabs (4 of them! Three new ones in Texas + refurbishing the Micron/IM Flash fab in Lehi, UT for 65nm + 45nm) so that should help; they appear to have become tired of relying on foundries so much and have taken matters into their own hands. Maybe that + a general trend of migrations to smaller nodes will free up enough capacity in the 300mm >28nm category.

GDS is a file format first used for taping out a design for manufacturing. It is not necessarily the case today but us older folks still use the term. The point is that down to 28nm other fabs can manufacture TSMC designs without major modifications. I was involved with one design at 40nm (as an IP vendor) that was manufactured at (4) different fabs. https://en.wikipedia.org/wiki/GDSII

FinFET is not the same as traditional CMOS since it's not planar but the process steps are similar. https://en.wikipedia.org/wiki/FinFET

My temporary chip shortage opinion is based on several things:
The fact that we did not have a chip shortage before Covid and we were not anywhere near full fab utilization, wafer manufacturers are optimizing mature nodes for maximum utilization so capacity is increasing, system companies are now designing their own chips and will do so on more available nodes, people are going back to work and will have less time and money to spend on electronics, inflation will also limit discretionary spending, and Covid is restricting other parts of the supply chain so there will be less focus on wafer manufacturing.

I would also note that the chip shortage is good for fabs since they are running at full utilization and prices are increasing.

Bottom line: The chip shortage narrative will continue until it completely falls apart with a demonstratable chip over supply which will trigger some type of a crash.
 
I don't know that I agree with the mature node supply/demand imbalance working out on its own... but I don't have any evidence to support that, other than pointing to projections of automotive electronics / IoT growth. On the other hand, TI is bumping up capacity in 300mm fabs (4 of them! Three new ones in Texas + refurbishing the Micron/IM Flash fab in Lehi, UT for 65nm + 45nm) so that should help; they appear to have become tired of relying on foundries so much and have taken matters into their own hands. Maybe that + a general trend of migrations to smaller nodes will free up enough capacity in the 300mm >28nm category.
TSMC also announced they are building a mixed 7nm and 28nm fab (as reported on this site: https://semiwiki.com/forum/index.php?threads/tsmc-to-build-new-fab-in-kaohsiung-taiwan.14940/) and one could argue that a mixed 5nm / 40nm could also "be possible", but not sure that it is economical to do a stand-alone 40nm fab. The tools that are required to make N7/6 FEOL are the same as 28nm (HKMG) FEOL, and most of the back-end also (minus, obv the EUV equipment which wouldn't be utilized). A question would be if there is sufficient "cycle time" while N5/4 wafers are going through EUV metalization steps to spin a few N40 wafers through the entire DUV process in parallel. Likely you would still need to configure a few of the dep-etch tools to the specific chemistry for the FEOL, but BEOL should be "share-able"?

TI OTOH was an IDM down to 45nm and then Fabless for 28nm and below. I don't recall if they attempted to make their 45nm compatible with any Foundry process to second source, which may be why they need to roll their own for increased production capacity. Certainly their 28nm (OMAP, from my personal experience) was multi-sourced by design.
 
TSMC also announced they are building a mixed 7nm and 28nm fab (as reported on this site: https://semiwiki.com/forum/index.php?threads/tsmc-to-build-new-fab-in-kaohsiung-taiwan.14940/) and one could argue that a mixed 5nm / 40nm could also "be possible", but not sure that it is economical to do a stand-alone 40nm fab. The tools that are required to make N7/6 FEOL are the same as 28nm (HKMG) FEOL, and most of the back-end also (minus, obv the EUV equipment which wouldn't be utilized). A question would be if there is sufficient "cycle time" while N5/4 wafers are going through EUV metalization steps to spin a few N40 wafers through the entire DUV process in parallel. Likely you would still need to configure a few of the dep-etch tools to the specific chemistry for the FEOL, but BEOL should be "share-able"?

TI OTOH was an IDM down to 45nm and then Fabless for 28nm and below. I don't recall if they attempted to make their 45nm compatible with any Foundry process to second source, which may be why they need to roll their own for increased production capacity. Certainly their 28nm (OMAP, from my personal experience) was multi-sourced by design.

There used to be two types of fabs I worked in: 200mm and 300mm. Now there are two types: EUV and non EUV. I have not been in an EUV fab yet but from what I hear they are a more expensive construct due to the EUV equipment requirements.
 
TSMC told major suppliers that they would build 6 Fabs. But I believe if Chip Acts subsidies amount is not as expected, TSMC will change their plan.
 
TSMC told major suppliers that they would build 6 Fabs. But I believe if Chip Acts subsidies amount is not as expected, TSMC will change their plan.

TSMC said on the last investor call that their CAPEX plans have not changed meaning they will spend a record $40-44B. Given that Intel is a big part of that CAPEX I would guess $44B and it will not go down next year.
 
The Fab shell TSMC is building in Arizona is a lot bigger than they need for 20k wpm, my expectation is they would be to ramp it up above 20k wpm before they build another shell. TSMC always builds extra clean room space.
Huh, interesting. How much do you think they have space for in the shell they are building? (not the other 5 spaces at the site)

Tom's Hardware had an article speculating on wafer capacity (for whatever that's worth) where they were saying the AZ fab is a "MegaFab" class (25kwpm capacity) rather than "GigaFab" (100kwpm capacity)
 
"dirt cheap" means several times cheaper than a new build fab, not tens of percent. Once the cost of the fab building and equipment have been paid off, the remaining costs (maintenance, supplies, labour, power, water...) are a fraction of the costs when new -- the exact numbers vary from node to node, but I guess at least 2x cheaper, maybe even more -- I'm sure Scotten Jones has data on this ;-)

40nm is far from dirt cheap, even with IP portability. With current tapeout prices, I guess even a new 40nm fab may make sense. I heavily underline that it only makes sense under CURRENT prices, and it takes a few years to build a fab.

On the other hand 130nm-180nm at 200mm wafer was mindbogglingly profitable for the last 7 years in a row, and will likely be in the future. 200mm fabs are now more profitable in fact than when 180nm was new. Why it will be profitable into the future? Because there will be no new, nor used 200mm equipment anymore!
 
40nm is far from dirt cheap, even with IP portability. With current tapeout prices, I guess even a new 40nm fab may make sense. I heavily underline that it only makes sense under CURRENT prices, and it takes a few years to build a fab.

On the other hand 130nm-180nm at 200mm wafer was mindbogglingly profitable for the last 7 years in a row, and will likely be in the future. 200mm fabs are now more profitable in fact than when 180nm was new. Why it will be profitable into the future? Because there will be no new, nor used 200mm equipment anymore!

China consumed the 200mm equipment which is still coming online. Once China becomes more semiconductor self sufficient prices will drop, absolutely.
 
Huh, interesting. How much do you think they have space for in the shell they are building? (not the other 5 spaces at the site)

Tom's Hardware had an article speculating on wafer capacity (for whatever that's worth) where they were saying the AZ fab is a "MegaFab" class (25kwpm capacity) rather than "GigaFab" (100kwpm capacity)
TSMC stated their initial capacity build is 20k wpm, I am not at my computer right now but I would think the clean room is sized for at least 40k wpm.
 
Huh, interesting. How much do you think they have space for in the shell they are building? (not the other 5 spaces at the site)

Tom's Hardware had an article speculating on wafer capacity (for whatever that's worth) where they were saying the AZ fab is a "MegaFab" class (25kwpm capacity) rather than "GigaFab" (100kwpm capacity)
OK, I went and looked, I think they could get up to 50k wpm of 5nm in the initial cleanroom plus on site they have room for 3 more cleanrooms.
 
TSMC also announced they are building a mixed 7nm and 28nm fab (as reported on this site: https://semiwiki.com/forum/index.php?threads/tsmc-to-build-new-fab-in-kaohsiung-taiwan.14940/) and one could argue that a mixed 5nm / 40nm could also "be possible", but not sure that it is economical to do a stand-alone 40nm fab. The tools that are required to make N7/6 FEOL are the same as 28nm (HKMG) FEOL, and most of the back-end also (minus, obv the EUV equipment which wouldn't be utilized). A question would be if there is sufficient "cycle time" while N5/4 wafers are going through EUV metalization steps to spin a few N40 wafers through the entire DUV process in parallel. Likely you would still need to configure a few of the dep-etch tools to the specific chemistry for the FEOL, but BEOL should be "share-able"?

TI OTOH was an IDM down to 45nm and then Fabless for 28nm and below. I don't recall if they attempted to make their 45nm compatible with any Foundry process to second source, which may be why they need to roll their own for increased production capacity. Certainly their 28nm (OMAP, from my personal experience) was multi-sourced by design.
I have been looking into this, there are couple of reports in the press in Taiwan but nothing from TSMC. There are press releases from TSMC about the Fab in Japan but I can't find anything about this fab. Also, 7nm and 28nm in the same fab makes no sense to me. TSMC's 7nm business is all migrating to their EUV based 7+/6nm process and I wouldn't think it would make sense to combine that with non EUV 28nm. Not sure I believe this is real.
 
Back
Top