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# Back of Envelope Wafer pricing based on TSMC Arizona Numbers

#### ZikaJan

##### New member
After following the discussion about wafer pricing for 3nm TSMC wafers in another thread, I did a back-of-the-envelope calculation based on the numbers TSMC released about their Arizona Investment, depreciation assumptions and an assumption on the split between facilities and equipment invest for the site.

Data Input: there will be \$40B investment for 600k WOPY.

Assumption 1: there is an 80/20 split between equipment and facilities (it is likely a bit higher for equipment, I used this more conservative estimate, as facilities/building depreciation is stretched over more years than equipment, resulting in less wafer cost from that portion)

Assumption 2: the depreciation for facilities is scheduled linearly for 20 years, for equipment it is either (2a) 5 years (standard?) or (2b) 8 years (extended)

Assumption 3: there are ~80 mask layers for an average \$25 cost per mask layer (not including depreciation and amortization, but including facilities, materials, labor), resulting in ~\$2k of operating cost per Wafer.

The high level cost model (CM) looks as follows:
• CM1: Based on Assumption 1+2a+3, the depreciation + operations cost per wafer is estimated \$13.3k
• CM2: Based on 1+2b+3 (using the extended depreciation of 8 years for the equipment), the total cost per wafer is \$9.3k

TSMC is reporting gross marging with Depreciation included in COGS, and Margin is defined as Margin = (Revenue - COGS / Revenue), so if we want to know revenue per wafer, we need to use the following formular:

Revenue = COGS/ (1-Margin)

TSMC's Q3'22 margin was 60.4%

Depending on what TSMC's Arizona Fab margin goals are, the total revenue per wafer would have to be between \$18.6k under CM2 and a 50% margin on the low side, and \$33k under CM1 and a 60% margin on the high side.

TSMC's major customers are likely paying less than the numbers above for their wafers as co-investment into new fab ramps would reduce their respective wafer costs. This might make comparison between TSMCs customers quite challenging, especially when we get only partial information from some of our industry contacts (e.g. just learning about what Apple pays per wafer, without accounting for potential co-investments).

Looking forward to feedback and a healthy discussion - I may have made mistakes in my formulas and assumptions, so corrections are very welcome.

#### Daniel Nenni

Staff member

Conclusion

The bottom line to all this is the cost for TSMC to make wafers in the US is only 7% higher than Taiwan if they built the same size fab complex in the US as what they have in Taiwan. Because they are building a smaller Fab complex the cost will be 17% higher but that is due to TSMC’s decision to build a smaller fab, at least initially.

I do want to point out this doesn’t mean the US is not at a bigger cost disadvantage versus any other country. India has reportedly discussed providing 50% of the cost of a fab as part of an attempt to get Taiwanese companies to set up a fab in India. At least in the past the national and regional governments in China have offered large incentives. Israel has also provided significant incentives to Intel in the past. But under current conditions a US fab is only 7% more expensive than a fab in Taiwan if all factors other than the location are the same.

#### Daniel Nenni

Staff member
Conclusion
The bottom line to all this is the cost for TSMC to make wafers in the US is only 7% higher than Taiwan if they built the same size fab complex in the US as what they have in Taiwan. Because they are building a smaller Fab complex the cost will be 17% higher but that is due to TSMC’s decision to build a smaller fab, at least initially.

I do want to point out this doesn’t mean the US is not at a bigger cost disadvantage versus any other country. India has reportedly discussed providing 50% of the cost of a fab as part of an attempt to get Taiwanese companies to set up a fab in India. At least in the past the national and regional governments in China have offered large incentives. Israel has also provided significant incentives to Intel in the past. But under current conditions a US fab is only 7% more expensive than a fab in Taiwan if all factors other than the location are the same.

It all depends on how much the US Government is subsidizing I guess and if TSMC gets CHIP Act money. But based on what I have heard thus far, TSMC building in AZ is nothing short of genius, absolutely. There is a big industry event tomorrow night. I will be there asking about TSMC AZ, absolutely.

### Dr. Morris Chang Exemplary Leadership Award​

The Dr. Morris Chang Exemplary Leadership Award recognizes individuals, such as its namesake, Dr. Morris Chang, for their exceptional contributions to drive the development, innovation, growth, and long-term opportunities for the semiconductor industry.

#### nghanayem

##### Well-known member
Speaking of wafer costs, I have always wondered what are the exact mechanisms behind the relationship of increasing capacity and decreasing wafer costs? Intuitively I know this, as well as knowing this to be a true piece of information. But what are the exact mechanics behind one TSMC fab in AZ (or any fab for that matter) having a higher cost per wafer than if the site had two fabs? Most of the costs that scale with capacity (tools, wafers, chems, staff, ect). I can't imagine it is just a "buying in bulk" advantage. For example, no matter how many wafers Samsung gobbles up every year, there is a limit to how low wafer makers will sell them to Samsung. Is it a matter of more wafers = more information turns = more yield learning? Any insight would be greatly appreciated.

Last edited:

#### ZikaJan

##### New member
There is the yield aspect yes, but there is also a capacity aspect.

At smaller fab sizes (like 20k WSPM), you have significant overcapacity in some areas - an equipment-side example: you may need 4 pieces of a specific type of equipment that can support 6k WSPM per piece of equipment - because 3 only get you to 18k, with 4 you however have overcapacity of 4k WSPM in that specific group, which is ~20% of capacity in the area. At 50k WSPM, the same tool family will need 9 pieces of equipment (8 only get you to 48), so again you will have 4k WSPM over-capacity in the tool group (now supporting 54k WSPM), but that is <10% overcapacity for that toolgroup.

Additionally you have to intentionally plan for more overcapacity for smaller toolgroups as there an unexpected tool-down-event will lead to much larger impact to the overall line capacity.

You have similar effects in the facilities area, but also in the engineering workforce.

#### cliff

##### Active member
20 years ago when wafers were small and yields were crappy (prior to the density rules of 90nm), die costs mattered.

Focus on 2.5D packaging and availability of MPWs, triple the wafer price. Eliminate the FPGA (or make it a fraction of the size) and the big PC board.

Ignore the bean counters, increase your prices and stand your ground. They will pay it. Think of the SIP, not the SOC.

#### cliff

##### Active member
Priorities IMO:
1) Avoid melting
2) Performance
3) Power of chips that don't melt
4) NRE
5) Time to market.... you may want to make this #2

and a way lower priority

6) Area/recurring cost.

OK, now throw your stick and stones

#### ZikaJan

##### New member
It all depends on how much the US Government is subsidizing I guess and if TSMC gets CHIP Act money. But based on what I have heard thus far, TSMC building in AZ is nothing short of genius, absolutely. There is a big industry event tomorrow night. I will be there asking about TSMC AZ, absolutely.

### Dr. Morris Chang Exemplary Leadership Award​

The Dr. Morris Chang Exemplary Leadership Award recognizes individuals, such as its namesake, Dr. Morris Chang, for their exceptional contributions to drive the development, innovation, growth, and long-term opportunities for the semiconductor industry.

Good point on the subsidies - at a rate of 30% co-investment by the government, the prices would go down to \$14.3K per wafer in a model with 8 year depreciation of the equipment and 50% GM.

#### jms_embedded

##### Active member
Good point on the subsidies - at a rate of 30% co-investment by the government, the prices would go down to \$14.3K per wafer in a model with 8 year depreciation of the equipment and 50% GM.
Where did you get 8-year depreciation of equipment? I haven't looked at TSMC's financial reports lately but IIRC they mentioned 4-5 year depreciation. Scotten Jones posted an article a while back (https://semiwiki.com/semiconductor-manufacturers/tsmc/303594-tsmc-arizona-fab-cost-revisited/) in which he stated:
Our models all calculate the capital investment by fab using a detailed bottoms-up calculation. The equipment, equipment installs, and automation are then depreciated over five years, the building systems over ten years and the building over fifteen years. We use these default values because most companies use these lifetimes for reporting purpose. There are lifetimes by country differences for tax purposes, but taxes and reporting values are typically calculated separately. There are some companies that don’t use five years for equipment but to enable consistent comparison between fabs we use five years as a default, although the ability to change the lifetimes is built into many of our Models.

#### ZikaJan

##### New member
I have seen both 5 and 8years in the past, and I agree 5 years sounds more realistic. My original post looked at both 5 year and 8year modelling, and 50% or 60% GM target

At 5 year depreciation, and 60% GM target, and assuming 30% government subsidies , the wafer price for a TSMC customer would still be around \$25k.

#### staf

##### New member
After following the discussion about wafer pricing for 3nm TSMC wafers in another thread, I did a back-of-the-envelope calculation based on the numbers TSMC released about their Arizona Investment, depreciation assumptions and an assumption on the split between facilities and equipment invest for the site.

Data Input: there will be \$40B investment for 600k WOPY.

Assumption 1: there is an 80/20 split between equipment and facilities (it is likely a bit higher for equipment, I used this more conservative estimate, as facilities/building depreciation is stretched over more years than equipment, resulting in less wafer cost from that portion)

Assumption 2: the depreciation for facilities is scheduled linearly for 20 years, for equipment it is either (2a) 5 years (standard?) or (2b) 8 years (extended)

Assumption 3: there are ~80 mask layers for an average \$25 cost per mask layer (not including depreciation and amortization, but including facilities, materials, labor), resulting in ~\$2k of operating cost per Wafer.

The high level cost model (CM) looks as follows:
• CM1: Based on Assumption 1+2a+3, the depreciation + operations cost per wafer is estimated \$13.3k
• CM2: Based on 1+2b+3 (using the extended depreciation of 8 years for the equipment), the total cost per wafer is \$9.3k
Also don't forget that most equipment has support contracts of around 20% annual cost of original price for the equipment and that wafer manufacturing also involves high cost chemicals consumables like photosensitive resists, CMP slurries, etc