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5nm wafer cost very high

Daniel Nenni

Admin
Staff member
The mask count from 10nm to 5nm was comparable according to TSMC (at IEDM 2019). The main point they made was they had expected many more masks at 5nm without EUV.
View attachment 252
That said, they do have special EUV mask handling in the fab (cleaning) due to lack of pellicles.

Thank you Fred. If not for EUV we would be using octuple patterning for 3nm?
 

Daniel Nenni

Admin
Staff member
In regards to IBS, I have very little regard for the accuracy of his numbers (Handel Jones). My experience is inside the semiconductor ecosystem as a working semiconductor professional not an analyst. I used to take IBS reports to chip companies for verification and it always ended up in laughter. He is fine for looking back at what design costs were but in regards to projecting future design costs IBS is ALWAYS on the high side.

Take a look at his reports over the years and you will see he is the chicken little of the semiconductor world. His strategy seems to be to throw out a big number so it get's sensationalized media coverage: As Chip Design Costs Skyrocket, 3nm Process Node Is in Jeopardy. Seriously? Gotta get those clicks, right?

Do these numbers jibe with yours?

“The industry needs to get a major increase in functionality as well as a small increase in transistor costs to justify the use of 3nm,” said Handel Jones, chief executive of International Business Strategies (IBS). “3nm will cost $4 billion to $5 billion in process development, and the fab cost for 40,000 wafers per month will be $15 billion to $20 billion.”

$300M for a 16nm design? In your report it is closer to $100M?

IBS Design Costs 20154.jpg

Source: IBS 2014
 

saifmk

New member
I used the latest analysis Handel Jones (IBS) released; see slide 8 here which suggests $100M for 16nm and $542M for 5nm. You're right that his older projection (shown in the chart you pasted) overshot 16nm compared to his newer backward looking estimate.

In my mind, the real issue is there is lots of heterogeneity depending on die size, chip type, etc. I've heard from someone in industry that the most expensive designs (e.g. for certain high-end CPUs) are higher than what's reported by IBS, but other designs (for some ASICs) are much lower. Curious to hear your thoughts on what the variation might look like.
 

Daniel Nenni

Admin
Staff member
Understood, but you must know that the 5nm design numbers from IBS are very high and will also be adjusted down, yet your report and the related sensationalized articles will remain.

I'm intimately involved with SoC and ASIC design (including AI chips), not CPU/GPU. Given that:

In regards to SoC design cost range: MediaTek is on the low side, Apple is on the high side, and QCOM is in the middle. The biggest difference is that Apple is a systems company and does not have the chip margin constraints that MediaTek and QCOM have. Meaning Apple spends a lot more on design than fabless chip companies. Google also spends more on design and Google doesn't sell chips or systems, it is all for internal use.

The chip design landscape is changing making it difficult for outsiders to forecast costs. But, if you want to average it out I would cut the IBS 5nm estimate in half for SoCs.

ASIC companies are even more margin constrained so they have the lowest design costs in the industry. ASIC companies also have more experience and automation than the average systems company they work for so I would cut the IBS 5nm estimate by 2/3rds.

So, it's not just the type of chip but also the company designing it. Sound reasonable?


I used the latest analysis Handel Jones (IBS) released; see slide 8 here which suggests $100M for 16nm and $542M for 5nm. You're right that his older projection (shown in the chart you pasted) overshot 16nm compared to his newer backward looking estimate.

In my mind, the real issue is there is lots of heterogeneity depending on die size, chip type, etc. I've heard from someone in industry that the most expensive designs (e.g. for certain high-end CPUs) are higher than what's reported by IBS, but other designs (for some ASICs) are much lower. Curious to hear your thoughts on what the variation might look like.
 

saifmk

New member
Sounds quite reasonable! Makes a lot of sense that there's heterogeneity across the board. FWIW, I want to be clear that our intent was *not* to be sensationalist -- we ran it by some experts before publishing and tried to extremely transparent about our methodology so that anybody can inspect it and see where they disagree; improve upon it; or decide that the methodology isn't appropriate at all. And the hope was useful discussion: I've found the discussion here useful, and I hope you feel the same. :)
 

Daniel Nenni

Admin
Staff member
You also need to take a closer look at yield, TSMC is not like the others.

When Apple came to TSMC at 20nm TSMC started doing yearly process nodes (half steps) with a focus on yield learning. TSMC freezes a process in Q4 so Apple can have HVM for the iProducts the next Fall without fail. Remember, Apple designs a very big die every year so yield is paramount. Not just for price but also for capacity (good die).

This was a completely new methodology for the foundry business and it really has made TSMC unique. For example, TSMC introduced double patterning at 20nm then added FinFETs for 16nm in the same fab. TSMC did a similar thing with EUV. They started adding EUV layers to a node already in production (7nm) then increased EUV layers at 6nm (same fab) and 5nm which resulted in a lot of yield learning.

Intel, for example, is much more traditional. They went to double patterning and FinFETs at 14nm and will go from zero EUV at 10nm to full EUV at 7nm.

This Apple/TSMC low risk/high yield process approach breaks with the traditional semiconductor yield curves so you really have to take that into account when making chip price approximations.

Yield numbers, like wafer prices, are highly confidential but if you were to use 90% yield as an approximation for TSMC HVM I doubt anyone would argue against it.
 

hskuo

Active member
Is this electrical yield? Or if not, what defect size is this measured at?
Fred: It is Test Vehicle "C"hip "P"robing Yield and use Foundry yield model to calculate D0. Why you ask about defect size? It might not be just so-call defects to kill yield.
 
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