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2nd A15 teardown (TSMC N5) from Angstronomics

Fred Chen

Moderator

This is an interesting and useful followup to the UnitedLex teardown posted earlier: https://semiwiki.com/forum/index.ph...-bionic-soc-n5p-details-from-unitedlex.15273/

A minimum pitch (fin, M0) of 28 nm is confirmed in this teardown, though not in the previous one from UnitedLex (there it looked >~40 nm).

So it looks like a mix of 28-40 nm pitches is possible on a given layer (fin or M0).

However, illumination supporting 28 nm pitch is mostly detrimental to the focus window of 40 nm pitch. So it is an expected multipatterning application.

28 nm and 40 nm pitch incompatibility.png
 
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benb

Active member
Fred terrific info and drawings.
Is the minimum area frequently derated/increased like this?
Asking more broadly, is it now conceivable that a N7 chip could pack more PPA than an N5 chip if it employed fewer or none of the area expansions you show above?
 

Fred Chen

Moderator
Fred terrific info and drawings.
Is the minimum area frequently derated/increased like this?
Asking more broadly, is it now conceivable that a N7 chip could pack more PPA than an N5 chip if it employed fewer or none of the area expansions you show above?
The article mentioned that single diffusion break (SDB) is becoming standard for other TSMC nodes (N6, N3), so would not have so much area given up as in the above case.
 

Daniel Nenni

Admin
Staff member

Fred Chen

Moderator
They are characterizing the N5 density based on a circuit design and that is in my opinion invalid. Scott has written about the problem before here: https://semiwiki.com/semiconductor-manufacturers/tsmc/285856-effect-of-design-on-transistor-density/ Scott bases his information on Techinsight data, this report used a System Plus sample cost model which is questionable at best.

Wrong approach, flawed data, click click click click..........
It looked like the same 60%NAND/40%SFF formula was used.
 

benb

Active member
I read the article, everyone on Semiwiki, read the article! Skyjuice is anonymous, which raises doubts. He/she writes like a process integration engineer, more of a scientist/engineer.
Some things I learned, super interesting:
New isolations: STI --> DDB --> SDB (and CNOD variant)
CNOD involves a gate-tie-down (to the power rail) which robs a lot of area.
TSMC N5 uses CNOD (Skyjuice indirectly alleges)
Skyjuice is using the Intel area metric, millions of transistors per square millimeter (MTs/mm2)
Skyjuice is also including the CPP (CGP) and MMP (but not tracks), so MTs/mm2 is no shell game; all the shells are turned over, except for tracks.
MTs/mm2 is used to illustrate the reduced area from high performance (3 fin) cells and CNOD on N5.
Intel has cobalt wrapped copper BEOL which is hinted at as being important for area as well, perhaps we will learn more in future articles
 
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Paul2

Active member
I read the article, everyone on Semiwiki, read the article! Skyjuice is anonymous, which raises doubts. He/she writes like a process integration engineer, more of a scientist/engineer.
Some things I learned, super interesting:
New isolations: STI --> DDB --> SDB (and CSOD variant)
CSOD involves a gate-tie-down (to the power rail) which robs a lot of area.
TSMC N5 uses CSOD (Skyjuice indirectly alleges)
Skyjuice is using the Intel area metric, millions of transistors per square millimeter (MTs/mm2)
Skyjuice is also including the CPP (CGP) and MMP (but not tracks), so MTs/mm2 is no shell game; all the shells are turned over, except for tracks.
MTs/mm2 is used to illustrate the reduced area from high performance (3 fin) cells and CSOD on N5.
Intel has cobalt wrapped copper BEOL which is hinted at as being important for area as well, perhaps we will learn more in future articles
What is CSOD? Is this how they call a non-COAG gate construction now?
 

benb

Active member
In the olden days, senior process integration engineers knew the whole integration and could explain all the decisions, all the trade-offs, in detail.
Now we have compartmentalization, NDAs, half-truths, and no person who can credibly parse the half truths.
Whether it’s true, partly true, or just an interesting fiction, what Angstronomics is doing here, comparing STI/DDB/SDB and the area affect of each, is at least a useful way to learn something about area effects of the integration; it doesn’t have to be 100% true to be useful.
 

tooLongInEDA

Active member
TSM counts chip density by 50%*(Logic)+30%*(SRAM)+20%(Analog). From TSMC Tech Symposium. FYI.
View attachment 820
That does seem more representative of real SoC usage than the Intel 60% NAND + 40% SDFF metric. Everything contains some SRAM.

Ideally, we would run a standard ARM core through the different processes to signoff and take the measurements. Perhaps in a few different power/performance/area optimisation scenarios. But this sort of information is not in the public domain.
 

Fred Chen

Moderator
The high-performance design rules are also relaxed relative to high-density. So density trends should only be used with same cell types.
 

Fred Chen

Moderator
The cell scaling from N7 to N5 is as below:
TSMC N7 to N5 cell scaling.png

Contacted gate pitch and cell height can be used to calculate the respective density increase.
Using the HD cell size, the N7 to N5 is density increase is 1.49x.
Using (HD) SRAM, 1.29x.
Using HP cell size, only 1.2x (cell height going from 300 nm to 280 nm).
Going from double to single diffusion break can bring an additional density enhancement.
 
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