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Do you know - was the latency problem at the silicon level was it the interfaces and ("software") protocols? I always wondered if it was just held back by the interface..
The problem was at the chip level, where read latency was about 350ns, which poorly compares to DRAM. I think write latency was in the range of 600ns. Write latency wasn't that important though, since Optane's endurance, while much higher than NAND, was not infinite like DRAM, and to enhance endurance Intel used a DRAM write cache managed by the memory controller.
Describe process of DRAM caching in Memory Mode using the Intel® Optane™ persistent memory specifically.
www.intel.com
The write cache also acted like a read cache, but even Intel admitted in the link above that "...workloads with highly random data access over a wide address range may see some performance difference versus DRAM alone." "Some performance difference"? It was manageable for desktops, but not datacenter servers.
Optane SSDs were another matter. Optane was awesome for storage, with higher performance than even SLC NAND, but the cost was far too high compared to typical MLC chips. Samsung, caught off-guard by Optane SSDs, competed by creating specialized SSDs with a NAND variation called Z-NAND, and Samsung designed a much higher-performance SSD controller, which helped close the gap somewhat with Optane SSDs. Intel's controller had higher latency. Though Optane SSDs were still the best available overall for performance, the very high cost of scaling the Optane chips vertically, called decks, made the storage price completely uncompetitive.
And the "market can be irrational for longer than you can be solvent" applies both ways. Very well doing companies outside of the hype circle might actually getting bad coverage, and correspondingly bad stock market life. The wider public is only getting input from the media, rather than the research on the ground.
Now the news that nanasheet FET has terrible thermals has surfaced in mass media, and Samsung is in hot water again, despite previously being lauded for getting RibbonFET early.
Wow, that's very terrifying...
Depending on the company, it may be excessively lifted or evaluated abnormally…
In some cases, there are companies that are extremly extremous and have had a cruelty of unfounded false rumors…
I feel sorry for the company...
The rumors that have arrived once can never be taken again, history is made from the studio... The truth will be disrupted...
And the "market can be irrational for longer than you can be solvent" applies both ways. Very well doing companies outside of the hype circle might actually getting bad coverage, and correspondingly bad stock market life. The wider public is only getting input from the media, rather than the research on the ground.
Now the news that nanasheet FET has terrible thermals has surfaced in mass media, and Samsung is in hot water again, despite previously being lauded for getting RibbonFET early.
Which news is this, and in what mass media? A reliable source or one which just repeats/misunderstands stuff picked up somewhere else dodgy?
Nanosheet/GAA has a bit worse thermals than FinFET -- if you want to be precise, the PMOS SHE is about the same, the NMOS was better in FinFET but in GAA is now similar to PMOS -- but this isn't a killer issue compared to the other advantages of GAA.
And before you say "that ain't so!" -- that's based on detailed thermal/self-heating analysis of real transistor-level layouts, not marketing waffle or speculation... ;-)
Which news is this, and in what mass media? A reliable source or one which just repeats/misunderstands stuff picked up somewhere else dodgy?
Nanosheet/GAA has a bit worse thermals than FinFET -- if you want to be precise, the PMOS SHE is about the same, the NMOS was better in FinFET but in GAA is now similar to PMOS -- but this isn't a killer issue compared to the other advantages of GAA.
And before you say "that ain't so!" -- that's based on detailed thermal/self-heating analysis of real transistor-level layouts, not marketing waffle or speculation... ;-)
This is especially true for Intel and Samsung, the two remaining advanced logic IDMs. Over the past one to two years, several fabless semiconductor companies and their products have performed very well.
Nanosheet/GAA has a bit worse thermals than FinFET -- if you want to be precise, the PMOS SHE is about the same, the NMOS was better in FinFET but in GAA is now similar to PMOS -- but this isn't a killer issue compared to the other advantages of GAA.
GAA + BSPD does sound like a significantly harder to cool solution than FinFET though? (+ Add 3D layers - curious if AMDs vcache will stay below the chip with GAAFET).
GAA + BSPD does sound like a significantly harder to cool solution than FinFET though? (+ Add 3D layers - curious if AMDs vcache will stay below the chip with GAAFET).
It is, but don't forget that part of the reason for GAA and BSPD are to reduce power consumption at the same clock speed, which pretty much cancels this out.
Of course if instead of this you keep the power per gate the same and put clock speed up, the power per mm2 will go up due to the higher density, and cooling will be a bigger problem. But that's true for every new node, the power per mm2 is gradually creeping up and up as the gate density and speed increases.
AMDs vcache will stay between the chip and the substrate, so the heatsink is next to the chip -- this is what they changed from the first-gen which had vcache on top and made CPU cooling worse, so they'd be crazy to go back to this. Anyway the I/O bumps are on the bottom of the die, and it's these that connect to the vcache.
www.intel.com
