Thanks for giving me the opportunity to do some math homework!
While the cost per transistor decreases with process advancements, fabless companies often prefer to pack more transistors into their designs to boost performance. If the transistor count remains the same with a new node, the cost savings benefit the fabless company rather than the end users. This doesn't provide much incentive for end users. A good example is Apple's SoC for iPhone, where die sizes have consistently been around 100 ± 15 mm² in recent years.
Now, let's compare Arrow Lake and Zen 5 using their top models.
The compute tile of the Core Ultra 9 285K (Arrow Lake-S) is 114.5 mm². The 8-core CCD of Zen 5 is 70.6 mm², and the 9900X/9950X models require two CCDs, totaling 141.2 mm².
141.2 / 114.5 = 1.233, meaning Zen 5 uses 23.3% more area for its top model compared to Arrow Lake.
The next question is cost, which is tricky to estimate. It's unclear which N4 node Zen 5 uses—N4, N4P, N4X, or even N4C (a cheaper version of N4P).
According to some reports, the price of N3 is 25% higher than N5. Considering N4 is close to N5 and has seen cost reductions over the years, we can assume the cheaper process cost for Zen 5 can offset the 23.3% larger area.
Additionally, AMD likely enjoys better loyalty discounts from TSMC than Intel. The smaller CCD die (70.6 mm² on N4 vs. 114.5 mm² on N3B) on a more mature node also brings yield benefits, translating to lower costs.
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