Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/biden-harris-administration-announces-chips-incentives-award-with-tsmc-arizona-to-secure-u-s-leadership-in-advanced-semiconductor-technology.21493/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Biden-Harris Administration Announces CHIPS Incentives Award with TSMC Arizona to Secure U.S. Leadership in Advanced Semiconductor Technology

Daniel Nenni

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FOR IMMEDIATE RELEASE
Friday, November 15, 2024

CHIPS Investment Incentivizes Creation of Leading-Edge Cluster in Phoenix, Arizona, and Over 20,000 Jobs; and Includes Commitment to Produce A16 Technology


Today, the Biden-Harris Administration announced that the U.S. Department of Commerce awarded TSMC Arizona Corporation (TSMC Arizona), a subsidiary of Taiwan Semiconductor Manufacturing Company Limited (TSMC), up to $6.6 billion in direct funding under the CHIPS Incentives Program’s Funding Opportunity for Commercial Fabrication Facilities. The award comes after the previously signed preliminary memorandum of terms, announced on April 8, 2024, and the completion of the Department’s due diligence. The award will support the company’s planned investment of more than $65 billion in three greenfield leading-edge fabs in Phoenix, Arizona. The Department will disburse the funds based on TSMC Arizona’s completion of project milestones.

“Two years ago, shortly after I signed the CHIPS & Science Act, I visited Arizona to announce a commitment by TSMC to invest in America, create American jobs, and shore up American supply chains. On that day, I spoke about how the United States invented semiconductors and used to manufacture nearly 40% of the world’s chips, but now makes closer to 10% of them and none of the most advanced chips. I came to office determined to change that, and we have since delivered on that promise, catalyzing nearly $450 billion in private investment in semiconductors, creating over 125,000 new construction and manufacturing jobs, and reshoring critical technologies to bolster our national and economic security,” said President Joe Biden. “Today’s final agreement with TSMC – the world’s leading manufacturer of advanced semiconductors – will spur $65 billion dollars of private investment to build three state-of-the-art facilities in Arizona and create tens of thousands of jobs by the end of the decade.

This is the largest foreign direct investment in a greenfield project in the history of the United States. The first of TSMC’s three facilities is on track to fully open early next year, which means that for the first time in decades an America manufacturing plant will be producing the leading-edge chips used in our most advanced technologies – from our smartphones, to autonomous vehicles, to the data centers powering artificial intelligence. Today’s announcement is among the most critical milestones yet in the implementation of the bipartisan CHIPS & Science Act, and demonstrates how we are ensuring that the progress made to date will continue to unfold in the coming years, benefitting communities all across the country.”

“The Biden-Harris Administration’s investment in TSMC Arizona is a turning point for American innovation and manufacturing that will strengthen our economic and national security,” said U.S. Secretary of Commerce Gina Raimondo. “The leading-edge chips that will be manufactured in Arizona are foundational to the United States' technological and economic leadership in the 21st century. Because of President Biden and Vice President Harris, the most advanced semiconductor technology on the planet will be made in America, creating thousands of jobs in the process.”

Through this investment in TSMC Arizona, the CHIPS Program Office is taking a significant step to strengthen U.S. economic and national security by helping to provide a reliable domestic supply of the chips that will underpin the 21st century technology economy, powering artificial intelligence (“AI”) and other fast-growing industries like high-performance computing, consumer electronics, automotive, and Internet of Things. At full capacity, TSMC Arizona’s three fabs are expected to manufacture tens of millions of leading-edge logic chips that will power products like 5G/6G smartphones, autonomous vehicles, and high-performance computing and AI applications. Early production yields at the first TSMC plant in Arizona are on par with similar factories in Taiwan.

The advanced chips that TSMC manufactures for its customers – including its A16 technology, which is the most advanced semiconductor technology in the world – are the backbone of central processing units (“CPUs”) for servers in large-scale datacenters and of specialized graphics processing units (“GPUs) used for machine learning. The Biden-Harris Administration’s investment is expected to create approximately 6,000 direct manufacturing jobs and more than 20,000 total unique construction jobs.

“Entering this phase of the U.S. CHIPS and Science Act marks a pivotal step in strengthening the semiconductor ecosystem in the United States,” said TSMC Chairman and CEO Dr. C.C. Wei. “TSMC appreciates the continual collaboration with customers, partners, local communities and the U.S. government beginning in early 2020. The signing of this agreement helps us to accelerate the development of the most advanced semiconductor manufacturing technology available in the U.S.”

For more information about TSMC Arizona’s award, please visit the CHIPS for America website.

In addition to the direct funding of up to $6.6 billion, the CHIPS Program Office will provide up to $5 billion of proposed loans – which is part of the $75 billion in loan authority provided by the CHIPS and Science Act – to TSMC Arizona under the award. As stated in the CHIPS Notice of Funding Opportunity for Commercial Fabrication Facilities, CHIPS for America will distribute direct funding to recipients for capital expenditures based on the completion of construction, production, and commercial milestones, and disburse loans to TSMC Arizona for amounts invested in capital expenditures. The program will track the performance of each CHIPS Incentives Award via financial and programmatic reports, in accordance with the award terms and conditions.

About CHIPS for America
CHIPS for America has awarded approximately $6.72 billion and allocated over $36 billion in proposed funding across 20 states and proposed to invest billions more in research and innovation, which is expected to create over 125,000 jobs. Since the beginning of the Biden-Harris Administration, semiconductor and electronics companies have announced over $450 billion in private investments, catalyzed in large part by public investment. CHIPS for America is part of President Biden and Vice President Harris’s economic plan to invest in America, stimulate private sector investment, create good-paying jobs, make more in the United States, and revitalize communities left behind. CHIPS for America includes the CHIPS Program Office, responsible for manufacturing incentives, and the CHIPS Research and Development Office, responsible for R&D programs, that both sit within the National Institute of Standards and Technology (NIST) at the Department of Commerce. Visit chips.gov to learn more.
 
The Trump Administration negotiated and brought TSMC to Arizona, and initiating the CHIPS Act legislation. The Biden Administration pushed the CHIPS Act through Congress after extensive negotiations and oversaw the application and approval process. None of this was easy.

With TSMC’s Phoenix fab phase one set to begin high volume production in December 2024 or January 2025, this marks a major achievement for the Trump and Biden administrations, the U.S. Congress, Arizona’s state and local governments, and TSMC.
 
The Trump Administration negotiated and brought TSMC to Arizona, and initiating the CHIPS Act legislation. The Biden Administration pushed the CHIPS Act through Congress after extensive negotiations and oversaw the application and approval process. None of this was easy.

With TSMC’s Phoenix fab phase one set to begin high volume production in December 2024 or January 2025, this marks a major achievement for the Trump and Biden administrations, the U.S. Congress, Arizona’s state and local governments, and TSMC.

CHIPs Act is acknowledged as bipartisan legislation. For anyone to imply differently is dishonest.

“The Biden-Harris Administration’s investment in TSMC Arizona is a turning point for American innovation and manufacturing that will strengthen our economic and national security,” said U.S. Secretary of Commerce Gina Raimondo. “The leading-edge chips that will be manufactured in Arizona are foundational to the United States' technological and economic leadership in the 21st century. Because of President Biden and Vice President Harris, the most advanced semiconductor technology on the planet will be made in America, creating thousands of jobs in the process.”

I would imagine Gina Raimondo will be replaced under the new administration.

Dishonest
adjective
1. behaving or prone to behave in an untrustworthy or fraudulent way:
 
I thought A16 wasn't coming to AZ for the foreseeable future. I think it's great that TSMC is building fabs in the US, but I think the Biden Administration is overselling what's being achieved. Process development is still in Taiwan.
 
I thought A16 wasn't coming to AZ for the foreseeable future. I think it's great that TSMC is building fabs in the US, but I think the Biden Administration is overselling what's being achieved. Process development is still in Taiwan.

TSMC has a N-1 strategy for AZ I am told. N4X, N3X, then N2P, roughly one year apart. Those processes are pretty much interchangeable. Unless TSMC AZ skips N2 which I highly doubt. I have not heard the AZ plan for A16 but I would guess that it is the same, especially if there is a CHIPS Act II.

Big customers want to be able to say they are buying TSMC wafers for the US, even though the majority might be from Taiwan. Minor details.

When TSMC brings HNA-EUV to the states that will require a new fab build so that may be delayed due to union problems :ROFLMAO:.
 
Just curious... are you sure the TSMC fabs aren't HNA ready?

From what I am told HNA-EUV systems are much bigger, heavier, and consume more resources. TSMC AZ fabs will have EUV systems installed so there is no reason to change them out for HNA-EUV. Moving fabs from N4 - N3- N2 is not an issue as it is the same equipment and those processes will be in use for many years to come. TSMC HNA-EUV will be a new fab build, my opinion.

I do not know, however, where Intel will build their first HNA-EUV fab. Maybe Ohio? I guess it depends on when HNA-EUV is fully qualified and ready for HVM. That could be past Ohio's due date. And if they move in EUV machines I highly doubt they will move them out and move HNA in. These systems are not portable nor interchangeable.
 
From what I am told HNA-EUV systems are much bigger, heavier, and consume more resources. TSMC AZ fabs will have EUV systems installed so there is no reason to change them out for HNA-EUV. Moving fabs from N4 - N3- N2 is not an issue as it is the same equipment and those processes will be in use for many years to come. TSMC HNA-EUV will be a new fab build, my opinion.

I do not know, however, where Intel will build their first HNA-EUV fab. Maybe Ohio? I guess it depends on when HNA-EUV is fully qualified and ready for HVM. That could be past Ohio's due date. And if they move in EUV machines I highly doubt they will move them out and move HNA in. These systems are not portable nor interchangeable.
High NA will fit into Intel fabs being built in Arizona. Hi NA is not the factor that will win the war IMO. In fact at we go to CFET in 6 years, it will be less important than stacking of CMOS. just an opinion

This is a huge win for the US semiconductor industry. Having Intel and TSMC 20 miles apart will be great for both companies and for tech workers. extremely important win for industry

So the question is ... how much Intel silicon will be run at TSMC AZ in 2026? How much Intel Silicon will be run at Fab 52 In 2026?
 
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CHIPs Act is acknowledged as bipartisan legislation. For anyone to imply differently is dishonest.

“The Biden-Harris Administration’s investment in TSMC Arizona is a turning point for American innovation and manufacturing that will strengthen our economic and national security,” said U.S. Secretary of Commerce Gina Raimondo. “The leading-edge chips that will be manufactured in Arizona are foundational to the United States' technological and economic leadership in the 21st century. Because of President Biden and Vice President Harris, the most advanced semiconductor technology on the planet will be made in America, creating thousands of jobs in the process.”

I would imagine Gina Raimondo will be replaced under the new administration.

Dishonest
adjective
  • 1. behaving or prone to behave in an untrustworthy or fraudulent way:

The funny thing is that Trump doesn't want to take the credit either despite his administration started the CHIPS Act legislation process. 🙂

Some critics might feel there are things they dislike or disagree with in the CHIPS Act and call it a bad law or a total failure. The problem is that if we look into any legislations passed in the US, there are always something some people don't like. There is no "perfect" legislation unless it's done under the greatest leaders Chairman Xi or President Putin.
 
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TSMC has a N-1 strategy for AZ I am told. N4X, N3X, then N2P, roughly one year apart. Those processes are pretty much interchangeable. Unless TSMC AZ skips N2 which I highly doubt. I have not heard the AZ plan for A16 but I would guess that it is the same, especially if there is a CHIPS Act II.
I highly doubt the toolset for A16 or even N2 will be basically the same as N5. There are many parts in a GAA and BSPD process flow that have no finFET analog. The only things that will likely be very similar to the point of interchangeability is many of the BEOL segments between N3/N3E/N2/FS metal layers for A16. With N5 and N3E likely sharing many (but not all) FEOL modules, and N2 and A16 sharing an identical FEOL. A good N3 vs N5 example is in the BEOL where a Ru liner is used on N3/N3E but not on N5, and extra multi patterning will need more ALD tools for spacer, more litho steppers, etchers, etc. etc. for a given number of wafer starts. A good N2/A16 vs N3E/N5 example is fin patterning. The GAA nodes will need the fins defined with direct print EUV to enable flexible device widths (at least if IMEC, IBM 2nm, SF3E, and SF3 are anything to go off of). The N5/N3 fins are instead made with ol'reliable (193i SAPQ). The N2/A16 fin loop will also have a bunch of EPI tools to build the Si-SiGe super lattice.

Now granted I am sure a decent percentage of the tools can be cross qualified, or that the same model of tool is used to do completely different things on node A and node B, but I bring it up because in many people's eyes an etcher is an etcher, an ALD tool is an ALD tool, etc, etc. However, this couldn't be further from the truth. A tool that is really good for one thing tends to be really bad (be that from the perspective of TCO or just raw process capability) when you tell it to do something it wasn't designed around. As I previously hinted at, the different process flows will drive different balances between tools will also be very different to support a given number of wafer starts. Additionally, different material choices will drive extra tools for handling/processing (either because older models can't effectively work with said materials or due to contamination issues preventing material A and B running on the same chamber similtanously).
Just curious... are you sure the TSMC fabs aren't HNA ready?
Since TSMC says TSMC AZ is CE! with Fab18, and at least visually seems to be using the same shell that was designed back in the 2010s I would highly doubt F21 P1-2 in AZ are high-NA capable. Maybe P3 will be built in a modified version to support it? But that only makes sense if they intend to run A14 and below in P3 (which from the sound of things would seem to only be on the cards for the eventual P4-6). As for F20 P1-4 in TW, it really depends on how far out the shell design was locked in and how long ago TSMC committed to not wanting to disrupt their BEOL or MEOL flows with a high-NA insertion on their first GAA and BSPDN nodes. Since shell designs are done WAY in advance, maybe it is possible that F20 will be high-NA capable? Not that it really matters since N2 and A16 won't be using high-NA. What we know for sure is that at least the latest phase of Fab 12 is high-NA capable since TSMC got their first tool, and that it is likely that the next generation of fab complexes TSMC makes for A14 and beyond production will almost certainly be build with the such that they can support them. What is unknown is if the latest fab 12 phases are one-off heavily modified derivatives of an old design (like D1X mod 3), is more or less unmodified from existing designs, or is a new forward-looking cleanroom design.

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High NA will fit into Intel fabs being built in Arizona. Hi NA is not the factor that will win the war IMO.
I wouldn't just pull random things out of your rear when you don't know definitively. It is a great way to end up with egg on your face.
In fact at we go to CFET in 6 years, it will be less important than stacking of CMOS. just an opinion
Maybe I just misunderstood with the way you typed it, but CFET is stacked CMOS. Also, you can take it to the bank that every CFET process will be using high-NA. IMEC talks about CFET in the early 2030s and all indications from industry and IMEC is to not relax device size like what happened with 3D NAND. A large part of the reason early 3D NAND backed off on lateral shrink was for device reliability and performance reasons. That same set of circumstances isn't hampering logic and there is no indication of many devices being stacked anytime soon (general industry momentum is around moving to 2D materials after the initial CFET move is made). If anything, CFET will require even more BEOL shrinks, as you now have the routing and power of two devices trying to be squeezed into the space of one.
This is a huge win for the US semiconductor industry. Having Intel and TSMC 20 miles apart will be great for both companies and for tech workers. extremely important win for industry
That benefit to workers is only the case once TSMC becomes a place that people actually want to stay working at. Hopefully it doesn't take long for TSMC Arizona to become a place you would actually want to work, but right now that place is for all intents and purposes radioactive (of course take it with a gain of salt because this is just anecdotes from me asking people if they would even consider the idea of working there and the observations of former TSMC co-workers). Moving off of that less than savory topic, I have to imagine the distance between TSMC all the way at the northern city limits and intel/microchip/infineon/NXP/etc being all the way in the south/southwest could make changing jobs to TSMC a pain (at least for people like me who really hate sitting in traffic/commuting).

1731733296865.png

(The route is between TSMC Fab21 and Intel Fab12-62, with green flags being manufacturing operations for other semiconductor makers that I remember existing in the area. Maybe I missed a couple, but I think this should be most if not all of them. I purposefully neglected to add the tool vendors because that would have taken actually all day.)
 
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From what I hear Intel 18A and PDK 1.1 is ready to rock and roll. Let's hope some big customers grab it.
That's a good news hope they listened to customers feedback.
Intel themselves will be going back to their own foundry for majority there is no doubt about it but the real wins are external customers to show progress and so far they are keeping it a secret
 
I highly doubt the toolset for A16 or even N2 will be basically the same as N5. There are many parts in a GAA and BSPD process flow that have no finFET analog. The only things that will likely be very similar to the point of interchangeability is the BEOL with N3/N3E/N2/FS metal layers for A16. With N5 and N3E likely sharing many (but not all) FEOL modules, and N2 and A16 sharing an identical FEOL. A good N3 vs N5 example is in the BEOL where Ru is used on N3 but not on N5, and extra multi patterning will need more ALD tools for spacer and more litho steppers for a given number of wafer starts. A good N2/A16 vs N3E/N5 example is fin patterning. The GAA nodes will need the fins defined with direct print EUV to enable flexible device widths and (at least if IMEC, IBM 2nm, SF3E, and SF3 are anything to go off of). The N5/N3 fins are instead made with ol'reliable (193i SAPQ). The N2/A16 fin loop will also have a bunch of EPI tools to build the Si-SiGe super lattice.

Now granted I am sure a decent percentage of the tools can be cross qualified, or that the same model of tool is used to do completely different things on node A and node B, but I bring it up because in many people's eyes an etcher is an etcher, an ALD tool is an ALD tool, etc, etc. However, this couldn't be further from the truth. A tool that is really good for one thing tends to be really bad (be that from the perspective of TCO or just raw process capability) when you tell it to do something it wasn't designed around. The balance between tools will also be very different to accommodate the different process flows and materials between those technologies.

Since TSMC AZ is CE! with fab18, and at least visually seems to be using a shell that was designed back in the 2010s I would highly doubt F21 P1-2 in AZ are high-NA capable. Maybe P3 will be built in a modified version to support it? But that is only if they intend to run A14 and below in P3 (which from the sound of things would seem to only be on the cards for the eventual P4-6). As for F20 P1-4 in TW, it really depends on how far out the shell design was locked in and how long ago TSMC committed to not wanting to disrupt their BEOL or MEOL flows with a high-NA insertion on their first GAA and BSPDN nodes. Since shell designs are done WAY in advance, maybe it is possible that F20 will be high-NA capable? Not that it really matters since N2 and A16 won't be using high-NA. What we know for sure is that at least the latest phase of Fab 12 is high-NA capable since TSMC got their first tool, and that it is likely that the next generation of fab complexes TSMC makes for A14 and beyond production will almost certainly be build with the such that they can support them. What is unknown is if the latest fab 12 phases are one-off heavily modified derivatives of an old design (like D1X mod 3), is more or less unmodified from existing designs, or is a new forward-looking cleanroom design.

View attachment 2467

I wouldn't just pull random things out of your rear when you don't know definitively. It is a great way to end up with egg on your face.

Maybe I just misunderstood with the way you typed it, but CFET is stacked CMOS. Also, you can take it to the bank that every CFET process will be using high-NA. IMEC talks about CFET in the early 2030s and all indications from industry and IMEC is to not relax device size like what happened with 3D NAND. A large part of the reason early 3D NAND backed off on lateral shrink was for device reliability and performance reasons. That same set of circumstances isn't hampering logic and there is no indication of many devices being stacked anytime soon (general industry momentum is around moving to 2D materials after the initial CFET move is made). If anything, CFET will require even more BEOL shrinks, as you now have the routing and power of two devices trying to be squeezed into the space of one.

That benefit to workers is only the case once TSMC becomes a place that people actually want to stay working at. Hopefully it doesn't take long for TSMC Arizona to become a place you would actually want to work, but right now that place is for all intents and purposes radioactive (of course take it with a gain of salt because this is just anecdotes from me asking people if they would even consider the idea of working there and the observations of former TSMC co-workers). Moving off of that less than savory topic, I have to imagine the distance between TSMC all the way at the northern city limits and intel/microchip/infineon/NXP/etc being all the way in the south/southwest could make changing jobs to TSMC a pain (at least for people like me who really hate sitting in traffic/commuting).

View attachment 2468
(green flags are the semiconductor makers that I remember having manufacturing operations out in AZ but maybe I missed a couple, and I neglected to add tool vendors because that would have taken actually all day)

"I have to imagine the distance between TSMC all the way at the northern city limits and intel/microchip/infineon/NXP/etc being all the way in the south/southwest could make changing jobs to TSMC a pain (at least for people like me who really hate sitting in traffic/commuting)."

To many Americans, a one-hour commute between home and work is something they dream of having. :)
 
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