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The suit alleges the DRAM suppliers made “supply decisions in unison” to restrict the supply of DRAM, thus inflating prices in 2016 and 2017, ultimately causing the critical memory product’s price to soar over the time period.
Samsung Electronics and SK Hynix have been sued in the United States for fixing DRAM prices.U.S. law firm Hagens Berman filed a consumer class-action lawsuit w
The suit alleges the DRAM suppliers made “supply decisions in unison” to restrict the supply of DRAM, thus inflating prices in 2016 and 2017, ultimately causing the critical memory product’s price to soar over the time period.
Samsung Electronics and SK Hynix have been sued in the United States for fixing DRAM prices.U.S. law firm Hagens Berman filed a consumer class-action lawsuit w
Okay, let's put it this way. This is kind of like how some firms sued HW over IP theft, and they never won. Eventually, they put HW on the entity list. It's fair for those who want to sue.
if HW embargo is justified then CXMT is justified.
CXMT will be able impact pricing by flooding a market, like China has with solar panels and would like to do with electric cars. CXMT will be losing money while they grow, but they don't care because it's all paid for. If they can scale their chips down to a good cost and make money or break even, then the other 3 have a huge problem. It would be sad to see Samsung and Hynix and Micron go out of business because a government is subsidizing market by flooding it. Korea and the US would probably be forced into subsidies.
This is a brand new phenomena for Micron, and US tech in general. Micron has not received any of that money yet. The Korean government has had their fingerprints on DRAM for a while now, especially SK Hynix.
This is a brand new phenomena for Micron, and US tech in general. Micron has not received any of that money yet. The Korean government has had their fingerprints on DRAM for a while now, especially SK Hynix.
I wouldn't get too excited about CXMT. We have seen this all before with YMTC i.e. years & years of press releases about impending capacity ramps but in the end not much is actually delivered.
In fact YMTC did finally get some momentum in 2021 but have since been hobbled by equipment bans. CXMT's job (building DRAM) was always going to be more difficult than YMTC's, so I'm not expecting any challenge to the big 3 for a while yet. That said, I'm sure the press releases will continue (-;
I wouldn't get too excited about CXMT. We have seen this all before with YMTC i.e. years & years of press releases about impending capacity ramps but in the end not much is actually delivered.
In fact YMTC did finally get some momentum in 2021 but have since been hobbled by equipment bans. CXMT's job (building DRAM) was always going to be more difficult than YMTC's, so I'm not expecting any challenge to the big 3 for a while yet. That said, I'm sure the press releases will continue (-;
CXMT's impact to global DRAM market is very limited, at least today. Future is hard to say.
CXMT has 2 fabs running production but all low end DRAM (18nm or equivalent to logic 10nm) which the big 3 was in production back in 2017/18. So CXMT's production node is at least 5 yrs behind the big 3, if not more.
However China domestic market still have huge demand for such lower end DRAM and thus CXMT's fabs are fully loaded (some China end user markets may be instructed by Chinese gov to use CXMT's devices despite its lower performance). Of course the higher end China markets for example PCs and mobile phones perhaps they cannot afford to compromise on performance and thus continues to buy large quantity advanced DRAMs from the big 3. CXMT's current fab outputs do not directly impact big 3's global market pricing.
Without any doubt CXMT is working on next generations, if not 1Beta (equivalent to logic 3nm), at least 1Alpha. If the US Gov does loosen or remove the current sanction which currently is at 18nm, you can bet CXMT will quickly and massively add capacity to flood the global market and attempt to push out one or two of the big 3's. Pathetically, cheap pricing has been and will continue to be their number 1 strategy to build dominance.
CXMT's impact to global DRAM market is very limited, at least today. Future is hard to say.
CXMT has 2 fabs running production but all low end DRAM (18nm or equivalent to logic 10nm) which the big 3 was in production back in 2017/18. So CXMT's production node is at least 5 yrs behind the big 3, if not more.
However China domestic market still have huge demand for such lower end DRAM and thus CXMT's fabs are fully loaded (some China end user markets may be instructed by Chinese gov to use CXMT's devices despite its lower performance). Of course the higher end China markets for example PCs and mobile phones perhaps they cannot afford to compromise on performance and thus continues to buy large quantity advanced DRAMs from the big 3. CXMT's current fab outputs do not directly impact big 3's global market pricing.
Without any doubt CXMT is working on next generations, if not 1Beta (equivalent to logic 3nm), at least 1Alpha. If the US Gov does loosen or remove the current sanction which currently is at 18nm, you can bet CXMT will quickly and massively add capacity to flood the global market and attempt to push out one or two of the big 3's. Pathetically, cheap pricing has been and will continue to be their number 1 strategy to build dominance.
This report presents Key DC characteristics for NMOS and PMOS transistors located in the word line drivers and sense amplifiers regions of the GigaDeviceHUANGSHAN4G die found inside the GDP1BFLM DDR3L SDRAM component extracted from a MiliankeMLK-CA03FPGA development board.
www.techinsights.com
The GDP1BFLM package contains a single 2 Gb CXMT G3 DDR3L SDRAM die. The DDR3L SDRAM (HUANGSHAN4G) die measures 6.26 mm × 6.31 mm (39.50 mm2) as measured from the die seals or 6.30 mm ×6.36 mm (40.07 mm2) for the full die. The die was manufactured using a DRAM CMOS process incorporating four back-end of line (BEOL) interconnect layers, one tungsten (W), two copper (Cu), one aluminum (Al), with bit line (BL) under capacitors and a buried word line (WL) forming the gate of the buried cell array transistor (BCAT).