Discussions with Dr. Kevin Zhang, SVP
Dr. Ian Cutress
Over the past year, I’ve had the chance to quiz every major foundry about their plans for the future. The latest in this series is TSMC, as part of their recent announcements around their roadmaps and upcoming process node technologies. As the world’s leading manufacturer of leading edge and EUV-based logic, as well as packaging the vast majority of the big AI chips, the pressure on TSMC to execute at speed and scale has only increased over the last few years. As part of their commitments to next-generation technologies, the company announced its A16 process node, Super Power Rail (the marketing name for its backside power delivery), ventures into co-packaged optics, and Silicon-on-Wafer technology, leveraging a demand for bigger substrates for the biggest chips. Here’s my latest video on these announcements.
Dr. Ian Cutress
Over the past year, I’ve had the chance to quiz every major foundry about their plans for the future. The latest in this series is TSMC, as part of their recent announcements around their roadmaps and upcoming process node technologies. As the world’s leading manufacturer of leading edge and EUV-based logic, as well as packaging the vast majority of the big AI chips, the pressure on TSMC to execute at speed and scale has only increased over the last few years. As part of their commitments to next-generation technologies, the company announced its A16 process node, Super Power Rail (the marketing name for its backside power delivery), ventures into co-packaged optics, and Silicon-on-Wafer technology, leveraging a demand for bigger substrates for the biggest chips. Here’s my latest video on these announcements.