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All that matters in the end is product performance and power. What node or number, what is the transistor count or what NA you got has bearing. All the noise in the world won’t matter if you don’t end up having a compelling product.
Intel wants to have leadership product and leadership technology and somehow it all starts with noise and videos and press about highNA. Have it and the rest will just fall in place ?
TSMC is making a ton of money, and Intel needs to make a lot of noise to get attention.. but the high NA unboxing at least shows they’re willing to take risks and push for the future. It’s also a rallying cry for the engineers.
I’ve also seen a few comments here on Semiwiki that even Intel 3 may have higher transistor performance than TSMC N3, and 18A will certainly beat TSMC N2 in some metrics. Remember there’s two races here: 1. The Lithography process itself, and 2. Volume/Capacity in the Foundry. Intel needs to win #1 first and it looks like they have a plan that is starting to bear fruit. We’ll know for sure in the next 9 months if we see Intel 3 and 20A launch in that time. #2 is going to be a very long game.
IMO, in the upcoming 9 months or even 2 years, the fruits in intel farm will be very bitter and sour, and expensive. When will it turn to be sweet and make money? intel might expect to be ~ 2030.
"Dave Zinsner, Intel chief financial officer, said, “This model is designed to unlock significant cost savings, operational efficiencies and asset value. As it begins to take hold, we expect to accelerate on our path toward achieving our ambition of 60% non-GAAP gross margins and 40% non-GAAP operating margins in 2030. Ultimately, improved cost competitiveness will help us deliver process technology, product and foundry leadership while driving significant financial upside for Intel and our owners.”
To prove 5N4Y, it should be by 12/31/2024 for the first 20A/18A wafer. The yield can not be guaranteed, and the effective volume (good chips shipped) is unknown now.
To prove 5N4Y, it should be by 12/31/2024 for the first 20A/18A wafer. The yield can not be guaranteed, and the effective volume (good chips shipped) is unknown now.
They claimed clearwater forest would be the first 18A product and would launch in 2025. They also showed a mock up at IFS-DC (mostly to show off their hybrid bonding tech). I doubt it will be larger volumes than a client part or even a P-core Xeon, but it is still an intel CPU at the end of the day. Unless we are talking some cannon lake type of flop I would assume at least in the millions of dies? Based on this diagram intel shared, 1M working dies makes ~83k chips. Blueone might have a better idea what sort of volumes are reasonable for a server part, but from my totally ignorant perspective that sounds easy enough to do. Add ontop of that the claim that panther lake client CPUs are also launching on 18A sometime later in 2025 (presumably around EOY like intel normally launches their client parts). And intel client parts are easy 10s of millions of unit sellers.
Why would they not? DUV and pitch splitting have been the starting points for fins, gates, and low level metals for a while. It is the cuts where they would switch to EUV. And possibly vias if those are not 193i multiple exposure combined with self-aligned structures, which may beat some EUV on cost.
Blueone might have a better idea what sort of volumes are reasonable for a server part, but from my totally ignorant perspective that sounds easy enough to do.
I'm not sure what the server CPU market looks like anymore. It used to be that server CPUs were about a 30 million unit market, give or take a few million. And x86 CPUs were about 99% of that. But AWS is installing a lot of Gravitons, Oracle is installing a lot of Ampere-based servers, and Microsoft is replacing Ampere (and probably a lot of x86 CPUs) with their upcoming Cobalt 100 CPU. And Google is doing Axion, also an Arm-based server CPU for Google Cloud. This tells me a really great Intel datacenter CPU would probably ship 10-15 million units. How low can the volume go and still be practical? I don't know.
“The cost is very high,” TSMC Senior Vice President Kevin Zhang said at a technology symposium in Amsterdam on Tuesday, referring to ASML’s latest system known as high-NA extreme ultraviolet. “I like the high-NA EUV’s capability, but I don’t like the sticker price.”
Zhang said the costs of running a factory, including construction, tools, electricity and raw materials, “keep going up.” “It’s a collective challenge for the whole industry,” he said.
No kidding, I spent $200 at the grocery store yesterday. Steak and lobster is getting pricey!
TSMC now has multiple Co Coo's now who are vying for CEO after CC becomes Chairman. It is called the Coo - Coo race internally. Kevin is one of the Co Coos. They are all PhDs so I think the tallest one should win.
TSMC can't use HNA EUV until it is full chip production ready and they have an ample amount of systems so maybe 2030?
I just watched a month old interview with Dr. Burn-Jeng Lin, one of the major contributors of immersion lithography. He was TSMC vice president of R&D until his retirement.
He said in addition to helping TSMC to adopt immersion lithography successfully, he changed TSMC's mindset about using newer machines/technology in manufacturing.
Dr. Lin said instead of using next generation of advanced machine to manufacturer the current generation of products, TSMC's attitude changed to using current generation of machine/technology to produce next generation of products.
This is a very interesting approach. It means in the TSMC's philosophy, if they can use the current EUV technology to make A16 with reasonable yield and cost, they will do it that way instead of High NA EUV.
