The reference was two masks for dual damascene, one for via one for trench.
??? Not sure I understand your point ("the reference" = this patent, or "the reference" = what this patent refers to as the norm, or something else?); the patent abstract and claims seem fairly clear about there being one mask and one etch step, with conventional lithography requiring two masks and two etches.
Here is the first claim:
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1. A method of manufacturing integrated circuit devices comprising:
providing a semiconductor substrate with a surface region, the surface region comprising one or more layers overlying the semiconductor substrate;
forming a copper layer overlying the surface region;
forming a dielectric layer overlying the copper layer;
forming a photoresist layer overlying the dielectric layer;
exposing a portion of the photoresist layer by placing a reticle over the photoresist layer and transmitting light from an exposing source to the photoresist layer, the reticle possessing at least two regions with different transmission rates, a first region of the reticle being used to create a via etch pattern in the photoresist layer and a second region of the reticle being used to create a trench etch pattern in the photoresist layer;
developing the photoresist layer, whereby a first portion of the photoresist layer is removed to expose a portion of the dielectric layer and a thickness of the second portion of the photoresist layer is formed; and
etching the photoresist layer and the dielectric layer in a single step to create a dual damascene pattern in the dielectric layer, wherein the ratio of a thickness of the first portion of the photoresist layer and a thickness of the dielectric layer is 1:1 and the ratio of the etch rate of the photoresist layer to the dielectric layer is 1:1.
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Anyway I just was wondering what is "normal" for dual damascene; I got the impression it was two masks (one for via one for trench, as you stated) but I have no idea what is typical.
Also from looking around at articles of the late 2000s / early 2010s, it seems like multiple patterning comes into the picture somewhere between 40nm and 22nm:
- (2007)
https://sst.semiconductor-digest.com/2007/01/asml-illuminates-a-dry-path-to-40nm/
The International Technology Roadmap for Semiconductors (ITRS) plots a route to 45nm half-pitch through water immersion lithography for critical levels, but customers of ASML have requested an alternative — one that employs familiar dry DUV exposure and the double pattern method being considered for 32nm. The company has responded with the XT:1450G, a version of its familiar 0.93NA Twinscan system speced to print 143 wafers/hour at 40nm double-patterning resolution.
- (2009)
https://semiengineering.com/euv-late-and-hurts/
The problem this time is the inability to etch fine enough lines with deep ultraviolet lithography. At 193nm, it doesn’t come close to providing the granularity needed at 32nm or 28nm, depending upon who’s defining the next process node. Immersion lithography doesn’t solve it either. That means the short-term solution is double patterning, which adds significantly to the mask cost, the time it takes to churn out wafers, and the overall cost of devices.
- (2010)
https://semiengineering.com/the-growing-legacy-of-moores-law/
In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing than a 193nm wavelength laser can etch at 22nm and beyond, and at present the only alternative is double patterning. As double patterning implies, it requires a double pass of the laser, as well as a much more complex mask set, and significantly more time and expense per wafer. Moving from 40nm NAND flash to 22nm will require six extra steps. With logic and DRAM, that same shift will require an extra 10 steps each.
- (2012)
https://people.eecs.berkeley.edu/~pister/147fa14/Resources/Intel22nm.pdf (C.H. Jan et al., Intel, IEDM 2012) -- the above references don't clarify whether they're talking about active/poly/metal layers; Intel's 22nm does, a bit:
This technology offers the flexibility of mixing and matching eight to eleven layers of low-k (LK) and ultra low-k(ULK) carbon-doped oxide (CDO) ILD stacks, as shown inFig. 14, for different SoC product segments. M1 employs double patterning to enable tight pitch and complex layouts.All other metal layers are fabricated with cost effective single patterning lithography. The tightest pitch layers are patterned with the self-aligned via (SAV) process with a sacrificial hard mask [5]. A 6um thick top metal layer is used for on-die power distribution and spiral inductors (Fig. 15). Density focused products employ up to six layers of minimum pitch(80nm) metal layers, while RC driven products are optimized for more relaxed pitcher layers (Table 2 and Fig. 16).
