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Samsung officially announced 10nm production last week with quite a bit of fanfare:
“Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology - World's First consumer product with the new 10nm FinFET process expected to be introduced in early 2017” Oct. 17, 2016
True, Samsung is the first do a 10nm press event (attached) but both TSMC and Intel are also in 10nm HVM.
Earlier this month TSMC announced 10nm high volume manufacturing (HVM) at their OIP conference in San Jose, CA. TSMC also discussed 10nm production in the Q3 investor call last week. To maintain high margins TSMC does not release processes to the manufacturing fabs until yield is stable at greater than 80%. The silicon reports I have heard discussed in the recent conferences puts TSMC 10nm yield at closer to 90%. Mediatek will deliver TSMC 10nm SoCs in the first half of 2017 and the Apple iPhone 8 will have a TSMC 10nm SoC in the second half of 2017. Since TSMC will use the same fabs for 7nm the transition from 10nm to 7nm in Q1 2018 will be incredibly fast so 10nm will be a quick node like 20nm was.
Intel is also in the 10nm race. It is interesting to note that Intel did not discuss 10nm on their most recent conference call leading to speculation that 10nm is not yielding. However that is not the case. The latest word is that Intel moved 10nm to their Israel fab and has begun HVM with greater than 80% yield. Intel is expected to deliver 10nm chips in the second half of 2018.
The 10nm process densities using the ASML “standard node” formula are as follows:
Intel 10nm 9.5nm
TSMC 10nm 11.3nm
Samsung 12.0nm
Which puts TSMC in the process lead today but Intel will recapture that lead in the second half of 2017 with their 10nm.
TSMC 7nm is rated by the ASML formula at 8.2nm which means TSMC will regain the lead in the first half of 2018 and remain in the lead until Intel and Samsung hit 7nm in the 2019-2020 time frame. TSMC 5nm will again beat Intel and Samsung 7nm in 2019 so the leap frogging continues.
GlobalFoundries is skipping 10nm to get their 7nm process out quickly. The plan is to begin risk production in the first half of 2018 putting them roughly six months behind TSMC.
The 7nm process densities using the ASML "standard node formula" are as follows:
Daniel, please be careful about using that particular table (generated by Scotten Jones). It's based on an assumption (which may not be correct in all cases) about what the "density increase factor" announced by foundries for their future nodes (without having exact numbers for CPP and MMP) actually means. If it includes a library shrink (smaller height, fewer tracks) then not all the increase comes from the process shrink (CPP*MMP), so the ASML "formula number" will be too small -- this has certainly happened in the past, and I'm sure will happen in the future since it makes the process look "better" -- though of course it does reflect the real density improvements that wil be seen when using the libraries, so it's not wrong. I've been in communication with Scotten about this, but I don't know if he plans to update the table (or has data to do so).
Daniel, please be careful about using that particular table (generated by Scotten Jones). It's based on an assumption (which may not be correct in all cases) about what the "density increase factor" announced by foundries for their future nodes (without having exact numbers for CPP and MMP) actually means. If it includes a library shrink (smaller height, fewer tracks) then not all the increase comes from the process shrink (CPP*MMP), so the ASML "formula number" will be too small -- this has certainly happened in the past, and I'm sure will happen in the future since it makes the process look "better" -- though of course it does reflect the real density improvements that wil be seen when using the libraries, so it's not wrong. I've been in communication with Scotten about this, but I don't know if he plans to update the table (or has data to do so).
Okay, I will talk to Scott. As you probably know I spend a lot of time with the different foundries and they have not objected to this formula. In fact they gave us feedback before it was published.
Do you feel published SRAM specifications are a better measure of process density?
Okay, I will talk to Scott. As you probably know I spend a lot of time with the different foundries and they have not objected to this formula. In fact they gave us feedback before it was published.
Do you feel published SRAM specifications are a better measure of process density?
There's nothing wrong with the ASML "process node" formula, so long as you have actual numbers for CPP and MMP. Where the table falls over is when a foundry says "density increase x.x times" (especially for future processes) and this is all allocated to CPP/MPP (process shrink) when in fact part of it is due to a circuit change (library shrink).
I don't think SRAM density is so helpful either -- which SRAM, one optimised for pure density but which is so slow (especially at lower voltages, and where minimum Vdd is high anyway) that it's effectively unusable for most real applications? Or the one that will mostly be used but where the density numbers don't look so good? This is another design choice, like library height, where isn't one good metric.
So for measuring "whose process is the most advanced" (as opposed to how much effort the library designers have put in and what tradeoffs they've chosen) the ASML one is the best I've seen, because in the end all the other sizes (RAM and libraries) depend on CPP and MMP.
It was my understanding that the A10x will be TSMC 10nm. TSMC 10nm is in HVM so there is no reason why it shouldn't unless Apple does not plan a new iPad this year. Last month Apple quietly upgraded the memory on some of the existing iPads and lowered the prices of some memory configs. A head fake?
I was really hoping for a new iPad announcement this month but we got a mediocre Mac upgrade instead. The iPad Pro was announced last September.
There's nothing wrong with the ASML "process node" formula, so long as you have actual numbers for CPP and MMP. Where the table falls over is when a foundry says "density increase x.x times" (especially for future processes) and this is all allocated to CPP/MPP (process shrink) when in fact part of it is due to a circuit change (library shrink).
I don't think SRAM density is so helpful either -- which SRAM, one optimised for pure density but which is so slow (especially at lower voltages, and where minimum Vdd is high anyway) that it's effectively unusable for most real applications? Or the one that will mostly be used but where the density numbers don't look so good? This is another design choice, like library height, where isn't one good metric.
So for measuring "whose process is the most advanced" (as opposed to how much effort the library designers have put in and what tradeoffs they've chosen) the ASML one is the best I've seen, because in the end all the other sizes (RAM and libraries) depend on CPP and MMP.
I agree on the SRAM. I was the foundry director for Virage Logic before they were acquired by Synopsys so I had an up close view of foundry process ramping and SRAM yields. Let's just say that the SRAMs used in process benchmark contests were not the ones used in production.
At about this time, there are some reports, probably still rumor-level, that 10nm from the respective companies are still not yielding that great. But it's still early and no rollout schedules affected (yet).
At about this time, there are some reports, probably still rumor-level, that 10nm from the respective companies are still not yielding that great. But it's still early and no rollout schedules affected (yet).
Two VERY unreliable sources....... Fake News....... Samsung did have 10nm yield problems last year but Intel and TSMC did not. I'm on my way to Taiwan today so I will have a fresh update next week. Intel has an investor call and an analyst meeting coming up so we should know where 10nm really stands.
Two VERY unreliable sources....... Fake News....... Samsung did have 10nm yield problems last year but Intel and TSMC did not. I'm on my way to Taiwan today so I will have a fresh update next week. Intel has an investor call and an analyst meeting coming up so we should know where 10nm really stands.
At the end of last year Samsung 10nm had single digit yields according to one of their major customers. This report caused some people to doubt TSMC 10nm as well but I have heard different. According to my sources (IP companies and two customers) TSMC 10nm is ramping fine. We will know more at TSMC Symposium next week so check back then. Myself and two other SemiWiki bloggers will be attending.
