Accelerating Connectivity with the Versal Adaptive SOC Network on Chip Workshop This workshop introduces the AMD Versal network on chip (NoC) to users familiar with other SoC architectures. Besides providing …
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About the webinar: With the growing demand for devices operating across multiple frequency bands, optimizing antenna radiation efficiency is essential for delivering reliable, high-performance connectivity. Join our webinar to discover how …
About this event Join industry experts from NTT Innovative Devices, Lumentum, and Keysight to discuss their historic demonstration of 448g / lane signaling over PAM4 — a cross-continental collaboration that’s …
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Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process by integrating Vitis IDE, Vitis Analyzer, and Vitis HLS into a single, …
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Featured Speakers: Kiran Vittal, Synopsys Ayush Goyal, Synopsys As System-on-Chip (SoC) designs become increasingly complex, ensuring reliable Design-for-Test (DFT) connectivity at the RTL stage is more important than ever. This …
As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will …
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Featured Speakers: Gustavo Pimentel, Principal Product Marketing Manager, Synopsys As edge, mobile and automotive applications demand faster data processing, lower latency, and reduced power consumption, PCI Express® 5.0 has emerged …
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Webinar date: 22.10.2025 | 9 AM CEST | 5 PM CEST Join our webinar and learn about the fundamentals of Gallium Nitride (GaN) technology and its applications in power systems. …
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Achieving Timing Closure in FPGA Designs Workshop Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, …
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Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices. This …
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Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx Parameterized Macros (XPM) for seamless synchronization. Join …
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Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with …
