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10 events found.

siemens

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Today
  • September 2025
  • Wed 10
    TAC 900.067 GBL WBNR BAT Automation Framework 800x450
    September 10 @ 2:00 AM - 3:00 AM

    Webinar: Benefit from standardization: Increase manufacturing efficiency with the Battery Automation Framework

    Online

    Discover how Siemens’ open, modular framework enables scalable, standardized automation for battery cell production Join us for an in-depth webinar exploring the transformative potential of Siemens' Battery Automation Framework — a cutting-edge, open, and modular toolkit designed specifically for the automation of battery production processes. This webinar will provide battery cell manufacturers with crucial insights …

    Continue reading "Webinar: Benefit from standardization: Increase manufacturing efficiency with the Battery Automation Framework"

  • Tue 16
    September 16 @ 3:00 PM - 4:00 PM

    Webinar: Powering Data Centers for the Future

    Online

    SICAM EPMS the future proven Solution for Power Management in Data Center This webinar is designed for technical engineers tasked with defining and implementing solutions for power management, power monitoring, and power quality within data center power supply systems. Explore the world of Electrical Power Management Systems (EPMS) for data centers. Learn about standardized, modular …

    Continue reading "Webinar: Powering Data Centers for the Future"

  • Tue 30
    Screenshot 2025 09 04 013215
    September 30 @ 9:00 AM - 10:00 AM

    Webinar: Hardware design of custom AI accelerators using High-Level Synthesis

    Online

    As the demand for Machine Learning increases, the need for custom hardware acceleration explodes. Hardware optimized for Performance, Power, and Area are incredibly important to stay competitive. This webinar will cover High-Level Synthesis and its benefits in quickly and accurately producing hardware accelerators. We will cover the step-by-step design and verification of the Wake Word …

    Continue reading "Webinar: Hardware design of custom AI accelerators using High-Level Synthesis"

  • October 2025
  • Thu 2
    Screenshot 2025 09 22 163523
    October 2 @ 12:00 PM - 1:00 PM

    Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet

    Online

    Ethernet speeds are accelerating fast and AI, Cloud, and HPC workloads are driving demand that doubles every year. With 800Gbps ports in production and 1.6Tbps Ethernet around the corner, the need for robust pre-silicon verification has never been greater. Join this webinar to see how the Veloce™ hardware-assisted verification platform extends support for 1.6Tbps Ethernet …

    Continue reading "Webinar: Enabling Tomorrow’s Workloads with 1.6Tbps Ethernet"

  • Tue 28
    Screenshot 2025 09 04 013215
    October 28 @ 9:00 AM - 10:00 AM

    Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis

    Online

    The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL, and performing verification. An agile workflow requires being able to iterate through the …

    Continue reading "Webinar: Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis"

  • Wed 29
    Screenshot 2025 09 23 153345
    October 29 @ 9:00 AM - 10:00 AM

    Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System

    Online

    As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift towards AI. Siemens EDA is leading this transformation by implementing a comprehensive strategy that combines machine learning, reinforcement learning, generative, and agentic AI across the …

    Continue reading "Webinar: Accelerating RTL-to-GDS digital implementation with generative and agentic AI: powered by Aprisa AI & the Siemens EDA AI System"

  • November 2025
  • Wed 5
    Screenshot 2025 10 29 071423
    November 5 @ 8:00 AM - 9:00 AM

    Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs

    Online

    High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS). Formal check tools are difficult to be analyzed on generated RTL (as the …

    Continue reading "Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs"

  • Tue 11
    Screenshot 2025 10 15 180018
    November 11 @ 9:00 AM - 10:30 AM

    Webinar: From RTL to Silicon: Qualcomm Closes the Power Gap with Module-Level Insights

    Online

    Traditional RTL low power design techniques such as sequential clock gating are widely deployed across the industry. Yet, even after multiple RTL revisions, residual power inefficiencies often remain undetected until silicon, resulting in missed optimization opportunities. This seminar presents a refined approach to conventional methodologies: a reporting and opportunity identification layer that sits atop clock …

    Continue reading "Webinar: From RTL to Silicon: Qualcomm Closes the Power Gap with Module-Level Insights"

  • Wed 12
    Screenshot 2025 10 29 071729
    November 12 @ 8:00 AM - 9:00 AM

    Webinar: Don’t Let VHDL Debugging Slow You Down! Use Questa One Sim

    Online

    Join us for this essential webinar where we'll explore how  Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity. We'll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively, and streamline your entire VHDL RTL debug workflow. This webinar is Part 1 of …

    Continue reading "Webinar: Don’t Let VHDL Debugging Slow You Down! Use Questa One Sim"

  • Tue 18
    Screenshot 2025 08 21 025131
    November 18 - November 20

    MASTER CLASS: Component-based transfer path analysis and virtual prototyping

    Leuven, Belgium Leuven, Belgium

    The Component-based TPA and Virtual Prototyping Master Class is a 3-day live training event that brings together the NVH community at the NVH facility in Leuven, Belgium. This immersive program features theoretical …

    Continue reading "MASTER CLASS: Component-based transfer path analysis and virtual prototyping"

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